Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMs

A sensing scheme in which the bit line is precharged to half V/SUB DD/ is introduced for CMOS DRAMs. The proposed circuitry uses a PMOS memory array and incorporates the following features: (1) a complementary sense amplifier consisting of NMOS and PMOS cross-coupled pairs; (2) clocked pulldown of the latching node; (3) complementary clocking of the PMOS pullup; (4) full-sized dummy cell generation of reference potential for sensing; (5) shorting transistor to equalize precharge potential of bit lines; and (6) depletion NMOS decoupling transistors for multiplexing bit lines. The study shows that the half-V/SUB DD/ bit-line sensing scheme has several unique advantages, especially for high-performance high-density CMOS DRAMs, which compared to the full-V/SUB DD/ bit-line sensing scheme used for NMOS memory arrays or the grounded bit-line sensing scheme for PMOS arrays in CMOS DRAMs.     

Observation of halo implant from the drain side reaching the source side and vice versa in extremely short p-channel transistors

The merging of halo implants from the drain side and the source side creates a maximum in the magnitude of the threshold voltage and thus a minimum in the off-current in the metal-oxide-semiconductor transistors. This paper demonstrates that the halo implant from the drain side can cross-over to the source side and vice versa for the look-ahead transistor test structures (transistor test structures with gate length smaller than that of the target transistor). The phenomenon of the cross-over of halo implant is more readily observed in PMOS transistors compared to NMOS transistors because for the same mask gate length, the effective channel length of PMOS transistor tends to be smaller than that of NMOS transistor. The advantage of the cross-over of halo implants can be understood as follows. Since the hole mobility is smaller than the electron mobility in silicon, PMOS transistor tends to have smaller on-current (I_on) than NMOS transistor. The on-current can be increased by using PMOS transistor with smaller mask gate length compared to the NMOS transistor. However, this approach will make the PMOS transistor very sensitive to the statistical variation in the gate electrode length during manufacturing. By making use of the above reported phenomenon, PMOS transistor can be made shorter without running into manufacturing control problem, resulting in bigger I_on but the penalty is that the I_off will become significantly higher.     

小尺寸NMOS和PMOS SEU敏感性对比分析

使用软件模拟的方法对NMOS和PMOS的单粒子翻转(SEU)特性进行份真,通过在阱内外碰撞的两种情况下对小尺寸NMOS和PMOS的SEU敏感性进行对比可知,对于深亚微米阶段相同工艺的器件,在阱外碰撞时,NMOS一定比PMOS对SEU敏感;但对于阱内碰撞,NMOS和PMOS对SEU的敏感性要视具体情况而定.     

基于PMOS型固态功率电子开关的宇航智能配电系统研究

针对当前使用NMOS固态功率电子开关的载人航天器智能配电系统存在NOMS隔离驱动控制电路占用大量硬件资源,且不能满足能源系统自主健康管理遥测信息采集需求的问题,文中提出了一种基于PMOS固态功率电子开关构建的智能配电系统设计方案。相对于NMOS,PMOS用于正线开关的非隔离驱动特性避免了配置隔离控制电路带来的系统资源代价问题,在简化硬件电路设计的同时获得了更多的遥测信息,解决了有限硬件资源与更多遥测参数需求的矛盾。针对SSPC负载短路保护特性带来的固态配电系统母线电压跳变问题,文中给出了提高固态配电器可靠性的辅助电路方案,可使负载短路保护故障不影响母线稳定。     

CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:Ni2Si, and Ni31Si12) on HfSiON

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni₃₁Si₁₂ FUSI gates on p-channel MOS (PMOS) with good V_t control to short gate lengths (L_G=50 nm, linear V_t of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NiSi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni₂Si or Ni₃₁ Si₁₂ on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni₂Si or Ni₃₁Si₁₂ FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% I_on improvement at I_off=100 nA/mum) was obtained for Ni ₃₁Si₁₂ compared to Ni₂Si FUSI gates, as well as a V_t reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS     

Roughness-enhanced reliability of MOS tunneling diodes

Both electrical and optical reliabilities of PMOS and NMOS tunneling diodes are enhanced by oxide roughness, prepared by very high vacuum prebake technology. For rough PMOS devices, as compared to flat PMOS devices, the Weibull plot of T_BD shows a 2.5-fold enhancement at 63% failure rate, while both the D₂ and H₂-treated flat PMOS devices show similar inferior reliability. For rough NMOS devices, as compared to flat NMOS devices, the Weibull plot of T_BD shows a 4.9-fold enhancement at 63% failure rate. The time evolutions of the light emission from rough PMOS and NMOS diodes degrade much less than those of flat PMOS and NMOS diodes. The momentum reduction perpendicular to the Si/SiO₂ interface by roughness scattering could possibly make it difficult to form defects in the bulk oxide and at the Si/SiO₂ interface by the impact of the energetic electrons and holes     

Strained CMOS Devices With Shallow-Trench-Isolation Stress Buffer Layers

In this brief, shallow-trench-isolation (STI) stress buffer techniques, including sidewall stress buffer and channel surface buffer layers, are developed to reduce the impact of compressive STI stress on the mobility of advanced n-type MOS (NMOS) devices. Our investigation shows that a 7% driving current gain at an NMOS device has been achieved, whereas no degradation at a p-type MOS (PMOS) device was observed. The same junction leakage at both the NMOS and PMOS devices was maintained. A stress relaxation model with simulation is thus proposed to account for the enhanced transport characteristics.     

CMOS compatible dual metal gate integration with successful Vth adjustment on high-k HfTaON by high-temperature metal intermixing

In this paper, we report for the first time a novel dual metal gate (MG) integration process for gate-first CMOS platform by utilizing the intermixing (InM) of laminated ultra-thin metal layers during high-temperature annealing at 1000 °C. In this process, an ultra-thin (2 nm) TaN film is first deposited on gate dielectric as a buffer layer. Preferable laminated metal stacks for NMOS and PMOS are then formed on a same wafer through a selective wet-etching process in which the gate dielectric is protected by the TaN buffer layer. Dual work function for CMOS can finally be achieved by the intermixing of the laminated metal films during the S/D activation annealing. To demonstrate this process, prototype metal stacks of TaN/Tb/TaN (NMOS) and TaN/Ti/HfN (PMOS) has been integrated on a single wafer, with WF of 4.15 and 4.72 eV achieved, respectively. Threshold voltage (V_th) adjustment and transistor characteristics on high-k HfTaON dielectric are also studied.     

The Effects of Mechanical Uniaxial Stress on Junction Leakage in Nanoscale CMOSFETs

This paper reports the influences of uniaxial mechanical stress on the reverse-biased source/drain to substrate junction leakage of state-of-the-art 65 nm CMOS transistors. For n-channel metal-oxide-semiconductor (NMOS) transistors, the band-to-band tunneling (BTBT) dominates the junction leakage current due to heavily doped junction and pocket implants. However, for p-channel metal-oxide-semiconductor (PMOS) transistors with embedded SiGe source/drain, the leakage current is found to result from both BTBT and generation current due to defects generated in the SiGe layer and at the SiGe/Si interface. A four-point bending technique is used to apply mechanical uniaxial stress on NMOS and PMOS devices along the longitudinal direction. It was found that the leakage current of both devices increases (decreases) with applied uniaxial compressive (tensile) stress, and that the strain sensitivity of the junction leakage of NMOS transistors is much weaker than that of PMOS transistors. By combining the bending technique with process strained Si (PSS) technology, additional stress was applied to NMOS and PMOS with high built-in stress to investigate the characteristics of junction leakage under extremely high uniaxial stress. It is shown that uniaxial tensile stress can both enhance the NMOS device performance and decrease the junction leakage. However, for the PMOS, there exists a tradeoff between boosting the transistor performance and decreasing the junction leakage current, so there is a limit in the amount of compressive stress that can be beneficially applied.     

Area-efficient layout design for CMOS output transistors

A novel layout design to effectively reduce the layout area of the thin-oxide NMOS and PMOS devices in CMOS output buffers with ESD consideration is proposed. With respect to the traditional finger-type layout, the large-dimension output NMOS and PMOS devices are realized by multiple octagonal cells. Without using extra ESD-optimization process, the output NMOS and PMOS devices in this octagon-type layout can provide higher driving/sinking current and better ESD robustness within a smaller layout area. The drain-to-bulk parasitic capacitance at the output node is also reduced by this octagon-type layout. Experimental results in a 0.6-μm CMOS process have shown that the output driving (sinking) current of CMOS output buffers in per unit layout area is increased 47.7% (34.3%) by this octagon-type layout. The HBM (MM) ESD robustness of this octagon-type output buffer in per unit layout area is also increased 41.5% (84.6%), as comparing to the traditional finger-type output buffer. This octagon-type layout design makes a substantial contribution to the submicron or deep-submicron CMOS IC's in high-density and high-speed applications     

Optimization of CMOS arbiter and synchronizer circuits withsubmicrometer MOSFETs

A convenient optimization method using a circuit simulator SPICE2 with realistic models for short-channel MOSFETs and capacitances is described. By using this method, MOSFET size optimization is carried out and it is found that the optimum size ratio of NMOS versus PMOS shifts from the simple theory of S. Flannagan (ibid., vol 20, p.880-2, 1985). NMOS size should be larger than PMOS size. This is due to the velocity saturation carriers in short-channel MOSFETs. The effects of the parasitic PMOS and NMOS sizes, supply voltage, and temperature are also considered. It is also shown that the symmetry of the cross-coupled NANDs and insertion of cascaded inverters do not help the optimization     

深亚微米CMOS管总剂量辐照特性的对比研究

对深亚微米NMOS和PMOS管进行了60Co γ总剂量辐射实验.实验结果表明,PMOS管在转移特性、噪声、匹配特性方面比NMOS管的抗辐照能力更强.对NMOS管和PMOS管的辐照损伤机理进行了理论分析.分析结果表明,不同的衬底类型导致了PMOS管和NMOS管的辐照效应的差异.基于实验与分析结果,提出了一些深亚微米模拟I...     

Punchthrough behavior in short channel NMOS and PMOS 6H-siliconcarbide transistors at elevated temperatures

An experimental investigation of the effects of high temperature on short channel NMOS and PMOS transistors in 6H-SiC is reported. Punchthrough characteristics are presented and examined at room temperature and 300°C. The punchthrough current increases dramatically for scaled PMOS transistors at high temperature while the temperature dependence of electrical characteristics for short channel NMOS is small. The results presented in this paper also provide insight into design criteria for short channel silicon carbide (SiC) devices intended for operation at elevated temperatures     

Radiation hardened by design techniques to reduce single event transient pulse width based on the physical mechanism

The impact of the source on single event transient (SET) is studied for the balanced two-transistor inverter by a novel simulation structure in a 90 nm twin-well bulk CMOS technology. Due to the significantly distinct mechanism of single event change collection in PMOS and NMOS, the source, which is beneficial to broadening P-hit SET pulse width (W_SET) but reducing N-hit W_SET, plays a different role in SET production. Based on these different source roles, different radiation hardened by design (RHBD) methods are proposed to reduce W_SET for PMOS and NMOS, respectively. The simulation results show that the proposed RHBD methods can remarkably reduce W_SET.     

Low-frequency noise characteristics in the MOSFETs processed in 65 nm technology

Low-frequency noise behavior in the MOSFETs processed in 65 nm technology is investigated in this paper. Low-frequency noise for NMOS transistors agrees with McWhorter''s theory (carrier number fluctuation), low-frequency noise in the sub-threshold regime agrees with McWhorter''s theory for PMOS transistors while it agree with Hooge''s theory (carrier mobility fluctuation) in the channel strong inversion regime. According to carrier number fluctuation model, the extracted trap densities near the interface between channel and gate oxide for NMOS and PMOS transistor are 3.94×10¹⁷ and 3.56×10¹⁸ cm^-3/eV respectively. According to carrier mobility fluctuation model, the extracted average Hooge''s parameters are 2.42×10^-5 and 4×10^-4. By consideration of BSIM compact model, it is shown that two noise parameters (NOIA and NOIB) can model the intrinsic channel noise. The extracted NOIA and NOIB are constants for PMOS and their values are equal to 3.94×10¹⁷ cm^-3/eV and 9.31×10^-4 V^-1. But for NMOS, NOIA is also a constant while NOIB is inversely proportional to the effective gate voltage. The extracted NOIA and NOIB for NMOS are equal to 3.56×10¹⁸ cm^-3/eV and 1.53×10^-2 V^-1. Good agreement between simulation and experimental results is achieved.     

Optimized sensing scheme of DRAMs

The half-V_cc sensing scheme of CMOS dynamic RAMs (DRAMs) has been analyzed. It has been found that fluctuations of the cell-plate bias must be taken into account since they can degrade the sense signal. An improvement is possible by connecting the bit lines to the cell plate and its half-V_cc generator during precharge. Optimum performance of the sense amplifier is achieved if the PMOS and NMOS latches are activated simultaneously. The advantages are: (1) the sensitivity is improved due to the elimination of the offset contribution caused by unmatched capacitive loads; (2) the sensing speed is enhanced due to faster sense signal amplification; and (3) the peak current is reduced since the NMOS latch does not lower the voltage level of both bit line and reference bit line     

Digital CMOS IC's in 6H-SiC operating on a 5-V power supply

A CMOS technology in 6H-SiC utilizing an implanted p-well process is developed. The p-wells are fabricated by implanting boron ions into an n-type epilayer. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells using a thermally grown gate oxide. The resulting NMOS devices have a threshold voltage of 3.3 V while the PMOS devices have a threshold voltage of -4.2 V at room temperature. The effective channel mobility is around 20 cm ²/Vs for the NMOS devices and around 7.5 cm²/Vs for the PMOS devices. Several digital circuits, such as inverters, NAND's, NOR's, and 11-stage ring oscillators are fabricated using these devices and exhibited stable operation at temperatures ranging from room temperature to 300°C. These digital circuits are the first CMOS circuits in 6H-SiC to operate with a 5-V power supply for temperatures ranging from room temperature up to 300°C     

多晶硅双栅全耗尽SOI CMOS器件与电路

对多晶硅双栅全耗尽SO I CM O S工艺进行了研究,开发出了1.2μm多晶硅双栅全耗尽SO I CM O S器件及电路工艺,获得了性能良好的器件和电路。NM O S和PM O S的阈值电压绝对值比较接近,且关态漏电流很小,NM O S和PM O S的驱动电流分别为275μA/μm和135μA/μm,NM O S和PM O S的峰值跨导分别为136.85 m S/mm和81.7 m S/mm。在工作电压为3 V时,1.2μm栅长的101级环振的单级延迟仅为66 ps。     

Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology

To provide area-efficient output ESD protection for the scaled-down CMOS VLSI, a new output ESD protection is proposed. In the new output ESD protection circuit, there are two novel devices, the PTLSCR (PMOS-trigger lateral SCR) and the NTLSCR (NMOS-trigger lateral SCR). The PTLSCR is in parallel and merged with the output PMOS, and the NTLSCR is in parallel and merged with the output NMOS, to provide area-efficient ESD protection for CMOS output buffers. The trigger voltages of PTLSCR and NTLSCR are lowered below the breakdown voltages of the output PMOS and NMOS in the CMOS output buffer. The PTLSCR and NTLSCR are guaranteed to be turned on first before the output PMOS or NMOS are broken down by the ESD voltage. Experimental results have shown that the PTLSCR and NTLSCR can sustain over 4000 V (700 V) of the human-body-model (machine-model) ESD stresses within a very small layout area in a 0.6 μm CMOS technology with LDD and polycide processes. The noise margin of the proposed output ESD protection design is greater than 8 V (lower than −3.3 V) to avoid the undesired triggering on the NTLSCR (PTLSCR) due to the overshooting (undershooting) voltage pulse on the output pad when the IC is under normal operating conditions with 5 V VDD and 0 V VSS power supplies.