点数可配置FFT处理器ASIC设计

本文提出了一种利用Radix-2² FFT算法实现的可配置点数的FFT处理器硬件实现结构。Radix-2² FFT算法最后一级碟形运算单元可以选择碟形1或者碟形1/碟形2,从而可以完成任意2n点FFT运算。据此提出可配置点数的FFT硬件结构,采用串行流水线单路延时置换结构,完成2048～256序列点数的可配置FFT处理器ASIC设计。芯片测试结果验证了基于Radix-2²算法的可配置点数FFT硬件结构可以完成4096～256点数频谱分析,4096点FFT计算时间少于90.02us,运算精度SQNR可以达到50.65dB,满足运用需求。     

微电子学、集成电路

TN4 2007010760并行数据FFT/IFFT处理器的设计/万红星,陈禾,韩月秋(北京理工大学信息科学技术学院电子工程系)//北京理工大学学报.―2006,26(4).―338～341.针对采用快速傅里叶变换(FFT)技术的多种应用场合,在分析基-2及基-4按时域抽取Cooley-Turkey算法特点的基础上,提出一种高性能FFT/IFFT处理器的硬件设计架构。通过改进基-4蝶形单元,可进行形如2的幂次方点数的FFT/IFFT运算。该结构能够并行地从4个存储器中读取蝶形运算所需操作数。仿真结果表明,该结构可以运用于对面积和速度要求较高的应用场合。图5表1参8     

一种按时间抽取的混合基实序列高效FFT算法

针对2N点实序列FFT的实现,分析了FFT运算的基本原理,并在基本原理的基础上介绍了一种按时间抽取的混合基FFT算法.此算法采用"包装"算法和基2-基4混合算法结合的方法进行运算.通过复杂度分析,显示了此算法与传统的单一基2或基4的FFT相比,大大减少了计算过程中所需的实加法的个数;当点数大于1024时,所需实乘法的个数也有所减少.这是一种实序列FFT的高效低复杂度算法.     

少模光纤通信频域均衡中的大点数FFT设计

为了减小频域均衡系统电路实现的功耗和面积,满足长距离少模光纤通信对均衡器的要求,对关键环节快速傅里叶变换(FFT)电路的实现进行了研究,采用2维分解算法将大点数的FFT运算转换为小点数FFT处理器的设计,降低了硬件复杂度。设计了基于现场可编程门阵列的高速蝶形运算核,实现了16384点FFT的2维R22SDF结构,提高存储器的资源利用率,减少了复数乘法器的使用;进行了理论分析和实验验证,取得了不同时钟频率下的电路结构占用资源的数据。结果表明,FFT运算器的正确性得到验证,该FFT运算器能够适应少模光纤通信系统中优化频域均衡电路结构的要求,能够实现200MHz数据传输速度的频域均衡实时处理。     

一种高精度的大点数二维FFT处理器设计

基于传统的频域抽取快速傅里叶变换(FFT)算法以及二维FFT算法,设计了一种高精度的大点数FFT处理器。该处理单元采用一个状态机控制整个运算流程,针对小点数情况的一维FFT算法和大点数情况的二维FFT算法,该处理器都可以智能地选择合适的处理流程和缓存管理,自动地完成整个FFT运算而无需软件介入。在支持大点数的二维FFT算法的基础上,该设计还通过对旋转因子计算过程的优化,以提高在大点数情况下的精度表现,在4M长度的输入序列时可以获得130 dB以上的信噪比。     

非2-基FFT的素因子算法研究

提出一种新的非2-基N点FFT的素因子算法.该方案与原素因子分解算法比较,实现了各个小点数DFT的同址顺序运算,并通过简单的地址模加运算得到顺序的输出,省去了多余的整序运算,是一种通用N点FFT算法.设计结构规整简单,利于硬件实现.以中国数字电视广播地面传输标准(DTMB)规定的3 780点FFT为例,结合WFTA算法和混合基算法,介绍了算法的具体设计与实现方案.     

超长点数FFT的设计与实现技术

随着宽带雷达系统所采用的信号带宽不断增加,为了实时完成脉冲压缩处理,需要进行超长点数FFT运算。本文提出一种超长点数FFT运算的实现方法。运用二维FFT算法,基于高性能FPGA处理平台,将超长点数FFT运算转换为两级短点数FFT的级联处理,并通过片外存储器解决片内存储资源有限的问题。实现结构上采用并行处理结构,显著提升了运算速度,可以实现在5ms内完成4M点数的FFT运算。实验结果表明,在相应的处理平台上,本文提出的超长点数FFT实现方法可以满足雷达系统的实时性需求,解决了宽带雷达实时脉冲压缩的关键问题。      

长度为2^n的FFT运算基实现

大点数FFT运算是数字信号处理中关键技术环节,本文提出一种大点数FFT运算基的实现,该实现是根据[1]中所提出的算法,结合寄存器阵列模块和重排序模块,实现FFT运算基模块内部的数据传输和模式切换,以基4与基2为模块中的基本运算单元构成大点数的FFT运算基,在控制电路配合下实现快速傅里叶变换。该实现通过面向寄存器级的Simulink仿真模型,验证本文所设计模块功能的正确性和可行性,为基于大点数的FFT运算指出了一种实现方法。     

WIMAX系统中可配置FFT/IFFT的设计与实现

针对WIMAX系统中变长子载波的特点,通过采用流水线乒乓结构,以基2、基4混合基实现了高速可配置的FFT/IFFT。将不同点数的FFT旋转因子统一存储,同时对RAM单元进行优化,节约了存储空间;此外对基4蝶形单元进行优化,减少了加法和乘法运算单元。仿真和综合结果表明,设计满足了WIMAX高速系统中不同带宽下FFT/IFFT的要求。     

高速并行FFT的FPGA实现

简要介绍了 FFT的分类,对比了其结构特点及实现复杂度,结合项目实现的需求,从中选择了一种适合 FP-GA高速并行实现的算法。在此基础上,推导了20点 FFT的实现方式,并且根据实际需求,可以采用此方法设计多种非基2FFT实现,甚至通过级联可完成大点数 FFT的设计实现,具有模块化、灵活可变的特点。结合 MATLAB仿真对FPGA实现结果进行了对比分析,并以图形化方式显示了对比结果,说明了方法可行、有效。     

Design of an FFT/IFFT Processor for MIMO OFDM Systems

In this paper, we present a novel 128/64 point fast Fourier transform (FFT)/ inverse FFT (IFFT) processor for the applications in a multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11n wireless local area network baseband processor. The unfolding mixed-radix multipath delay feedback FFT architecture is proposed to efficiently deal with multiple data sequences. The proposed processor not only supports the operation of FFT/IFFT in 128 points and 64 points but can also provide different throughput rates for 1-4 simultaneous data sequences to meet IEEE 802.11n requirements. Furthermore, less hardware complexity is needed in our design compared with traditional four-parallel approach. The proposed FFT/IFFT processor is designed in a 0.13-mum single-poly and eight-metal CMOS process. The core area is 660times2142 mum² , including an FFT/IFFT processor and a test module. At the operation clock rate of 40 MHz, our proposed processor can calculate 128-point FFT with four independent data sequences within 3.2 mus meeting IEEE 802.11n standard requirements     

基于802.11a的FFT/IFFT处理器设计

设计了一种应用于802.11a的64点FFT/IFFT处理器.采用单蝶形4路并行结构,提出了4路并行无冲突地址产生方法,有效地提高了吞吐率,完成64点FFT/IFFT运算只需63个时钟周期.提出的RAM双乒乓结构实现了对输入和输出均为连续数据流的缓存处理.不仅能实现64点FFT和IFFT,而且位宽可以根据系统任意配置.为了提高数据运算的精度,设计采用了块浮点算法,实现了精度与资源的折中.16位位宽时,在HJTC 0.18μmCMOS工艺下综合,内核面积为:0.626 7 mm2,芯片面积为:1.35 mm×1.27 mm,最高工作频率可达300 MHz,功耗为126.17 mW.     

New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy

The paper proposes a new continuous-flow mixed-radix (CFMR) fast Fourier transform (FFT) processor that uses the MR (radix-4/2) algorithm and a novel in-place strategy. The existing in-place strategy supports only a fixed-radix FFT algorithm. In contrast, the proposed in-place strategy can support the MR algorithm, which allows CF FFT computations regardless of the length of FFT. The novel in-place strategy is made by interchanging storage locations of butterfly outputs. The CFMR FFT processor provides the MR algorithm, the in-place strategy, and the CF FFT computations at the same time. The CFMR FFT processor requires only two N-word memories due to the proposed in-place strategy. In addition, it uses one butterfly unit that can perform either one radix-4 butterfly or two radix-2 butterflies. The CFMR FFT processor using the 0.18 /spl mu/m SEC cell library consists of 37,000 gates excluding memories, requires only 640 clock cycles for a 512-point FFT and runs at 100 MHz. Therefore, the CFMR FFT processor can reduce hardware complexity and computation cycles compared with existing FFT processors.     

基于多核处理器BWDSP1042的FFT性能优化

博微DSP1042(BWDSP1042)是我国自主研发的一款高性能数字信号处理器.现阶段,由于BWDSP硬件计算资源和访存带宽限制,通过调优快速傅里叶变换(Fast Fourier Transform,FFT)算法结构运算时间仍可减少.基于高性能多核BWDSP1042体系架构以及指令编排原则,优化了基-2FFT算法结构...     

An efficient locally pipelined FFT processor

The fast Fourier transform (FFT) is a very important algorithm in digital signal processing. The locally pipelined (LPPL) architecture is an efficient structure for FFT processor designing in a real-time embedded system. Two basic building blocks, to the LPPL FFT processor, the butterfly in pipeline, and address generating, are discussed in this brief. Based on the "deep" feedback to butterfly-2, a novel approach for pipelined architecture, the radix-2 single-path deep delay feedback architecture is proposed. For length-N discrete Fourier transform computation, the dominant hardware requirements are minimal for complex multipliers log/sub 4/N-1 and adders 2log/sub 4/N. As an integral need of the LPPL FFT processor design, address generating and coefficient store-load structures are also presented.     

A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems

This paper presents a new dynamic voltage and frequency scaling (DVFS) FFT processor for MIMO OFDM applications. By the proposed multimode multipath-delay-feedback (MMDF) architecture, our FFT processor can process 1-8-stream 256-point FFTs or a high-speed 256-point FFT in two processing domains at minimum clock frequency for DVFS operations. A parallelized radix-2⁴ FFT algorithm is also employed to save the power consumption and hardware cost of complex multipliers. Furthermore, a novel open-loop voltage detection and scaling (OLVDS) mechanism is proposed for fast and robust voltage management. With these schemes, the proposed FFT processor can operate at adequate voltage/frequency under different configurations to support the power-aware feature. A test chip of the proposed FFT processor has been fabricated using UMC 90 nm single-poly nine-metal CMOS process with a core area of 1.88 times1.88 mm² . The SQNR performance of this FFT chip is over 35.8 dB for QPSK/16-QAM modulation. Power dissipation of 2.4 Gsample/s 256-point FFT computations is about 119.7 mW at 0.85 V. Depending on the operation mode, power can be saved by 18%-43% with voltage scaling in TT corner.     

基于FPGA的32位浮点FFT处理器的设计

介绍了一种基于FPGA的1024点32位浮点FFT处理器的设计。采用改进的蝶形运算单元,减小了系统的硬件消耗,改善了系统的性能。详细讨论了32位浮点加法器/减法器、乘法器的分级流水技术,提高了系统性能。浮点算法的采用使得系统具有较高的处理精度。     

WFTA算法的FPGA设计与实现

Winograd傅里叶变换算法（WFTA）利用旋转因子W的特性对其进行分解,能够把FFT运算中乘法次数降到最低,是一种高效且资源占用相对较少的FFT实现方法。以256点分解为两维16×16点的小数组WFTA进行运算为例介绍了大数组WFTA算法的FPGA设计与实现方案。仿真测试表明,所设计的256点FFT处理器,乘法器资源消耗仅为基-2FFT的1/2、基-4FFT的2/3,且在100 MHz主时钟频率下完成运算仅需5.8μs,满足FFT处理器的高速实时性要求。     

An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor

Fast Fourier transform (FFT) plays an important role in the orthogonal frequency division multiplexing (OFDM) communication systems. In this paper, we propose an area-efficient design of variable-length FFT processor which can perform various FFT lengths of 512/1,024/2,048/4,096/8,192 points used in OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting-handheld (DVB-H). To reduce computational complexity and chip area, we develop a new variable-length FFT architecture by devising a mixed-radix algorithm that consist of radix-2, radix-2² and radix-2/4/8 algorithms and optimizing the realization by substructure sharing. Based on this architecture, an area-efficient design of variable-length FFT processor is presented. By synthesized using the UMC 0.18 μm process, the area of the processor is 2.9 mm² and the 8,192-point FFT can be performed correctly up to 50 MHz with power consumption 823 mW under a 1.8 V supply voltage.

流水线结构FFT/IFFT处理器的设计与实现

针对实时高速信号处理的要求，设计并实现了一种高效的FFT处理器。在分析了FFT算法的复杂度和硬件实现结构的基础上，处理器采用了按频率抽取的基—4算法，分级流水线以及定点运算结构。可以根据要求设置成4P点的FFT或IFFT。处理器可以对多个输入序列进行连续的FFT运算，消除了数据的输入输出对延时的影响。平均每完成一次N点FFT运算仅需要Ⅳ个时钟周期。整个设计基于Verilog HDL语言进行模块化设计。并在Altera公司的Cyclone Ⅱ器件上实现。