The finite element modelling of laser soldering for electronic assemblies

The laser provides a controllable means of supplying localized energy for solder joint formation and is a valuable tool in electronics manufacture. The modelling of heating behaviour in typical structures requires consideration of many different phenomena and the resulting models can become complex. The work described here shows that, given appropriate modelling assumptions, finite element models are able to give accurate predictions of heating in high-pin count devices as well as a valuable insight into the important factors affecting the success of laser soldering operations. In particular, it is shown here that conduction through the body of the component being soldered does not significantly affect heating of the solder but that variations in copper track thickness can result in a doubling of the required soldering time. In addition, it is shown that conduction through the printed circuit board is important when using a scanned laser beam to solder multiple joints. Copyright © 2002 John Wiley & Sons, Ltd.     

Crank‐shaped and Y‐shaped through‐hole interconnections filled with Au‐Sn solder

Crank‐shaped and Y‐shaped through‐hole interconnections (THI) filled with Au‐Sn solder are demonstrated in this study. They are expected to realize a higher‐density wafer‐level package (WLP) for electrical devices including the fields of MEMS (Micro Electro‐Mechanical Systems) and MOEMS (Micro Optical Electro‐Mechanical Systems) compared with conventional WLP using THI consisting of straight through‐holes. In this paper, formation techniques for crank‐shaped and Y‐shaped THI are described. In order to make crank‐shaped and Y‐shaped through‐holes in a substrate, both femtosecond laser irradiation and wet chemical etching are used. Crank‐shaped through‐holes with an 80‐μm opening and 400 μm deep have also been achieved. Gold (Au)‐tin (Sn) solder was filled into the holes using the molten metal suction method (MMSM). Airtightness of the THI was examined using the helium leakage test, and the estimated leakage rate was less than 1.0 × 10^?9 Pa·m³/s, which is sufficient for use in WLP applications. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 179(1): 54–62, 2012; Published online in Wiley Online Library ( wileyonlinelibrary.com) . DOI 10.1002/eej.21134     

Rapid die heating for low-stress die attach

During traditional isothermal die attach assembly, significant thermomechanical stress develops in the solder joints between the die and board. The coefficient of thermal expansion (CTE) of the silicon die and the woven composite circuit board materials are widely different. Under isothermal die attach, there is, hence, a mismatch between the thermal expansion displacements of the die and substrate, thereby leading to stress in the solder joints and die interconnect layers. One avenue to alleviate these stresses is to use alternate die attach processes that rely on localized heating of the die and solder joints so as to minimize the thermal expansion displacement mismatch. Die attach stress can be reduced significantly through rapid die heating (RDH), which results in the die being hotter than the board at the solder solidification point. Analytical modeling shows that RDH can reduce residual stress by up to 80% compared to traditional, isothermal die attach processing. Limited experimental results demonstrate 40% stress reduction to date. This paper will detail these results and physical analysis of the resulting solder joints.     

Influence of internal mechanical stress and strain on electricalperformance of polyethylene electrical treeing resistance

Crosslinked polyethylene (XLPE) and low-density polyethylene (LDPE) insulations used in HV cables are not only subjected to electrical and thermal stresses, but also exposed to mechanical stresses, whether residual internal stresses created during the cooling process of the fabrication, external forces when cables are bent during installation or thermomechanical stresses caused by differential thermal expansion between the conductor and the polymeric material. In order to investigate the possible influence of mechanical stresses on dielectric properties of polyethylene, measurements were conducted on pin-plane XLPE and LDPE samples with various magnitudes of residual mechanical stresses around the embedded electrode. The time to inception, the growing rate and the shape of the electrical trees under different voltages are reported in this paper. Specimens with the highest values of residual stresses were found to have the shortest inception times and the longest trees after one hour of aging under different voltages. When the mechanical stress was allowed to relax, the treeing resistance was measured to be significantly improved     

Automated X‐ray inspection method for fillet‐less mounted chip components

Chip components mounted on the printed circuit board are rapidly being miniaturized. Furthermore, the fillet‐less chip soldering technique, which does not use a solder fillet, is widely used in portable products such as mobile phones. However, there is no method to inspect the soldering of fillet‐less chip mounting. In this paper, we propose an automated X‐ray inspection technique for fillet‐less chip mounting. It extracts three inspection parameters from the X‐ray image. In the experiments, we evaluate the repeatability and inspecting ability of the technique and confirm that sufficient information for failure detection is obtained. An automated X‐ray inspection system using this technique is now in operation at some factories, so in conclusion our automated method would be useful in practice. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

芯片封装参数对功率模块热特性影响的研究

由于温度分布不均匀以及封装中各层材料之间的热膨胀系数不同,使功率模块在工作中产生交变的热应力,造成焊层疲劳、键合线脱落等失效形式,因此研究模块的热特性尤为重要。热的测量是电力电子系统中最困难的工作之一,对封装结构进行电-热-力精确的仿真分析,能够准确了解对器件不同部位的温度、应力分布。采用基于电-热-力多物理场的有限元仿真,研究了封装材料、封装参数和封装结构对功率器件的温度、热阻、热应力这些热特性的影响,为优化封装设计,最终提高功率模块可靠性提供了一定的参考。     

Numerical analysis on thermal characteristics for chip scale package by integrating 2D/3D models

The objective of this paper is to investigate stress and strain of a special scale package‐substrate on chip for reliability evaluation or manufacture strategy in deep‐seated situation. A two‐dimensional model with one‐half of cross‐section (2D model) and a three‐dimensional model with one‐fourth of whole package (3D model) were built, respectively, to simulate the thermal stress and strain of CSP‐SOC under the condition of the standard industry thermal cycling temperature −40 to125°C. The different locations can be processed by using the two models, respectively, based on different modeling simplified modes. By using 2D model, the numerical simulation shows that the maximum deformation of the prototype occurs in printed circuit board (PCB), the maximum stress and strain occurs in the outer solder balls. In the meantime, by the results of 3D model, the simulation shows that the maximum elastic strain occurs in the interface between the solder balls and PCB, the minimum strain occurs in the underfill tape, the maximum packaging stress occurs in the edge area of the chip. The result from 3D model maybe more impersonal to reflect the stress and strain characteristics because the third direction is considered in modeling. The analysis by integrating the 2D model and 3D model can get a more comprehensive profile for the thermal investigation of chip scale package (CSP) than by using any single model. The investigation built a basis for improving reliability in engineering design of CSP product. Copyright © 2008 John Wiley & Sons, Ltd.     

计及焊层疲劳影响的风电变流器IGBT模块热分析及改进热网络模型

针对不同疲劳寿命时期对风电变流器绝缘栅双极型晶闸管(IGBT)模块结温的影响,分析焊层在不同脱落度下的IGBT模块热阻变化规律,并建立考虑热阻变化的改进热网络模型。首先,依据风电机组变流器IGBT模块的结构和材料属性,建立三维有限元热-结构耦合分析模型,对基板焊层和芯片焊层在不同脱落度下IGBT模块结温和热应力的分布规律进行仿真分析。其次,确定不同焊层脱落度下其热阻增量值,并建立IGBT模块改进热网络模型。最后,将三维有限元模型和改进热网络模型的结温计算结果进行对比分析,验证了所提的改进热网络模型的有效性。     

一种大型电器触头电阻钎焊工艺试验

介绍了THW2-4000低压万能式断路器静触头的电阻钎焊工艺试验过程。并简单说明了温度、压力、焊接面粗糙度、钎料厚度等工艺参数对焊件钎着率及钎焊质量的影响。     

Void-induced thermal impedance in power semiconductor modules: some transient temperature effects

The operation of power semiconductor modules creates thermal stresses that grow voids in the solder die-attach layer. These voids reduce the ability of the die-attach solder layer to conduct heat from the silicon junction to the heat spreader. This results in increased thermal impedance. The effect of accelerated aging on solder bond voiding and on thermal transient behavior is investigated. Commercially packaged TO-247 style MOSFETs are power cycled, imaged, and thermally analyzed to generate a correlation between void percentage and thermal impedance.     

Fuzzy Logic-based Electrothermal Life Model for Inverter-fed Induction Motor Insulation

Pulse width modulated adjustable speed drives used in industries lead to significant advantages in terms of performance, size, and efficiency. But, the output voltage and the current waveforms become non-sinusoidal leading to an increase in voltage and thermal stresses. This results into accelerated insulation aging and premature failure of the motors. With multiple stresses, the life models for insulating materials become complex and ambiguous. This article presents the fuzzy logic application to derive an electrothermal life model to investigate the synergic effects of voltage and thermal stresses on intrinsic aging of inverter-fed induction motor insulation. Three parameters, viz. voltage stress factor, waveform slope stress factor, and spike frequency factor, are proposed to describe the insulation stresses for pulse width modulated voltages. These parameters are computed from the experimental results at different switching frequencies and are used in fuzzy logic-based life estimation algorithms. The results of the fuzzy logic life model are verified by performing the accelerated aging test with the same pulse width modulated voltages on paper insulation. An electrothermal life model is derived from the fuzzy logic results, which can be directly used for the life estimation of any general purpose low-voltage inverter-fed induction motor insulation.     

Interface microstructure evolution of lead-free solder on Ni-based under bump metallizations during reflow and high temperature storage

The interface microstructure interaction between SnCuAg Pb-free solder and three different Ni-based alloys under bump metallization (UBM) systems are studied using transmission electron microscopy (TEM). Ni reacts with Sn-rich Pb-free solder swiftly and is consumed readily by Pb-free solder. Thermally stable intermetallic compounds at the solder/UBM interface such as Cu/sub 6/Sn/sub 5/ or Ni/sub 3/P are necessary to protect Ni from being penetrated by Pb-free solders. Interface microstructure study reveals the potential process and reliability issues when applying Pb-free solders on existing UBM systems. Cu/Ni(V)/Al, can be used for Pb-free solder with marginal thermal budget. Au/Ni(V)/Ti/Al, is not suitable for Pb-free solder. And Au/eNi(P)/Al, is the most suitable for Pb-free solder and shows best thermal stability.     

基于改进Cascade RCNN算法的电路板缺焊检测

现阶段工业生产线,多类型电路板焊接无法采用自动化器械。针对贴片元器件人工焊接存在缺焊的现象,为了减少工厂因返工而造成的人力和物力损失,提出通过机器视觉技术对贴片元器件焊接情况进行自动检测。使用改进的ResNet-FPN结构,将浅层特征信息进行多尺度通道融合,从而增加了微小目标和遮挡目标特征信息的丰富性,减少了训练参数,加快了网络训练的前向速度;通过引入焦点损失（Focal loss）,平衡了分类样本数量,减小了损失值。实验结果表明,改进的Cascade RCNN算法训练速度稍快于原始模型,召回率小幅度提高,平均精度均值（mAP）达到90.9%,比原始模型提高了2.2个百分点,取得了更好的检测效果。     

全膜电容器低熔点刮擦焊料性能的研究

全膜电容器已成为电力电容器的发展方向,而铝箔外凸式电极结构又是其最佳选择。本文主要介绍新研制成功的铝钎焊用低熔点焊料的优良性能。用于全膜电容器,对进一步提高电容器的性能将会发挥重要作用。     

T91/12Cr1MoV异质接头焊接残余应力模拟与分析

T91/12Cr1MoV异质接头广泛应用于热电厂主蒸汽管线。由于母材及焊材金属性能的差异,导致该异质接头中会产生较大的焊接残余应力,常常会引起早期失效。利用有限元软件ABAQUS,采用热力顺次耦合的计算程序,对主蒸汽管中T91/12Cr1MoV异质接头的焊管外表面和熔合线方向的焊接残余应力分布进行了模拟,并分析了焊后热处理对焊接残余应力的影响。结果表明,热处理前,焊接残余应力峰值位于管道外表面焊缝两侧的焊接热影响区,其中,以T91侧热影响区的应力峰值最高。焊后热处理可以有效降低焊接热影响区的残余应力峰值,且对12Cr1MoV侧热影响区残余应力的改善效果明显优于T91侧热影响区。     

机械应力作用下电工钢片静态磁滞特性模拟方法研究

准确快速模拟磁性材料在不同应力下的磁滞特性对设计承受机械应力的电气设备铁心有重要意义。用BROCKHAUS-MPG200电工钢测试系统,测量了电工钢片样本在不同应力下的磁滞回线,发现其在应力作用下,磁滞回线会产生局部畸变的现象,且磁密越高,这种畸变越严重。为此,首次将2种常用的简化Preisach模型拓展至应力下的电工钢片磁滞特性模拟,发现仅有一种Priesach模型适用。根据该模型的基本特征,仅需利用具有畸变特性的实测极限磁滞回线,即可辨识不同应力值下的Everett函数。提出立方插值法提取以应力为变量的逆Everett函数,建立了应力下电工钢片的静态逆Preisach模型。实验及仿真结果表明,该模型计算精度较高,可用于实际工程中应力下磁性材料的磁滞特性模拟及磁滞损耗计算。     

机械应力作用下电工钢片静态磁滞特性模拟方法研究

准确快速模拟磁性材料在不同应力下的磁滞特性对设计承受机械应力的电气设备铁心有重要意义。用BROCKHAUS-MPG200电工钢测试系统,测量了电工钢片样本在不同应力下的磁滞回线,发现其在应力作用下,磁滞回线会产生局部畸变的现象,且磁密越高,这种畸变越严重。为此,首次将2种常用的简化Preisach模型拓展至应力下的电工钢片磁滞特性模拟,发现仅有一种Priesach模型适用。根据该模型的基本特征,仅需利用具有畸变特性的实测极限磁滞回线,即可辨识不同应力值下的Everett函数。提出立方插值法提取以应力为变量的逆Everett函数,建立了应力下电工钢片的静态逆Preisach模型。实验及仿真结果表明,该模型计算精度较高,可用于实际工程中应力下磁性材料的磁滞特性模拟及磁滞损耗计算。     

Change in Magnetic Domain Structure of Nd‐Fe‐B Sintered Magnets by Compressive Stress

To clarify the relationship between compressive stresses and demagnetization of Nd‐Fe‐B sintered magnets, we have examined the change in domain configuration by compressive stresses using a Kerr microscope. The magnetic domains of five kinds of Nd‐Fe‐B sintered magnets have been observed. The magnets have a coercivity of 0.8 MA/m to 1.4 MA/m and residual magnetic flux density of 1.3 T to 1.5 T. Irreversible demagnetization of Nd‐Fe‐B magnets with a low coercivity of 0.875 MA/m and high residual magnetic flux density of 1.41 T to 1.47 T have occurred from applying a compressive stress of 100 MPa. The compression‐affected area is approximately 0.14%. The stress more than 50 MPa is needed to demagnetize Nd‐Fe‐B magnets. The amount of irreversible demagnetization depends upon the intensity of the compressive stress as well as the residual magnetic flux and coercive force of the magnets.     

The role of microscopic defects in multistress aging of micaceousinsulation

The aging mechanism of mica/epoxy insulations under multiple stresses is investigated with both breakdown tests and a scanning electron microscope (SEM). The result of simultaneous multistress testing shows that thermal and mechanical stresses have a synergistic effect on electric life. Similar results are also obtained for residual electrical breakdown characteristics after sequential application of thermal aging and mechanical stress. It is confirmed with SEM pictures that thermal stress causes isolated delaminations at the mica/epoxy interface. Using a newly developed SEM apparatus with servomechanisms, the development of delamination and cracks are observed during mechanical fatigue tests in realtime. A multistress aging model is proposed with relation to the generation and development of the microscopic defects     

平面接触型铜铝过渡设备线夹的大气腐蚀行为

为了解铜铝过渡设备线夹在工业大气污染环境下的运行状况,采用次亚硫酸钠＋氯化钠水溶液盐雾试验,模拟研究了铜铝过渡设备线夹的大气腐蚀行为,探讨了大气腐蚀对线夹电学性能的影响.结果表明,铜铝过渡设备线夹大气腐蚀产物主要由铝、锡、铅的硫酸盐及水溶性氯化物组成.腐蚀初期,主要以氯离子对铝/锡铅钎料界面铝板表面氧化膜的点蚀为主;腐蚀后期,主要以次亚硫酸根对铝/锡铅钎料界面两侧的整体腐蚀为主,直至沿此界面裂开.腐蚀初期,铜铝过渡设备线夹的电阻率变化不大;腐蚀2天后,其电阻率大幅上升.研究结果对于线夹运行管理具有参考意义.