Modeling pentode-like characteristics of recessed-gate staticinduction transistor

A new analytical model is described for the pentode-like region of the characteristics of recessed-gate SIT structures. The model allows one to investigate the transition from saturating characteristics of long channel JFET's to nonsaturating behavior of SIT devices, taking into account realistic device geometry     

A device model for the amorphous-silicon staggered-electrodethin-film transistor

A model for the amorphous-silicon (a-Si) staggered-electrode thin-film transistor (TFT) that incorporates gate-voltage dependent mobility for channel current and space-charge-limited current effects for the source and drain contacts is discussed. This model is in excellent agreement with TFT data over a wide range of applied voltages and for various channel lengths. For the devices measured, the TFT current depends more sensitively on effective channel mobility than on space-charge-limited current through the a-Si layer, but the latter is responsible for current crowding at low drain voltage. Because of the two-dimensional current flow under the contacts, their equivalent lumped element model exhibits a different power law behaviour than that for one-dimensional current flow in an n⁺-i-n⁺ structure. It also shows that a peak in the differential conductance curve at low drain voltage is a sensitive indicator of current crowding and implies a superlinear equivalent lumped element in series with the intrinsic TFT     

基于纳米多晶硅薄膜晶体管分裂漏MAGFET制作和特性

A split-drain magnetic field-effect transistor （MAGFET） based on a nano-polysilicon thin film transistor （TFT） is proposed, which contains one source, two drains and one gate. The sensor chips were fabricated on （100） high resistivity silicon substrate by CMOS technology. When drain-source voltage equals 5.0 V and length and width ratio of the TFT channel is 80 μm/160 μm, the current and voltage magnetic sensitivities of the split-drain MAGFET based on the TFT are 0.018 mA/T and 55 mV/T, respectively. Through adopting nano-polysilicon thin films and nano-polysilicon thin films/high resistivity silicon heterojunction interfaces as the magnetic sensing layers, it is possible to realize detection of the external magnetic field. The test results show that magnetic sensitivity of the split-drain MAGFET can be improved significantly.     

Characteristics of field-effect transistor using fluorinated amorphous-silicon (a-Si:F)

Thin-film field-effect transistors are fabricated by use of fluorinated amorphous-silicon alloy (a-Si:F) containing no hydrogen. The characteristics of transistors such as on-off current ratio are comparable to those of hydrogenated amorphous-silicon transistors and are unchanged after 600°C annealing.     

Fabrication and characterization of a new EEPROM cell with spacer select transistor

In this letter, process technology and cell characteristics of a newly developed compact electrically erasable programmable read only memory cell are described. The cell has spacer select gates on both side walls of floating gate and this gives a very small cell size as well as relief of topology during contact formation. The cell size is 0.95 /spl mu/m/sup 2/ with 0.18 /spl mu/m logic process. The cells are programmed and erased by Fowler-Nordheim tunneling. It appears that programming requires 3 ms at 16 V while erasing requires 2 ms at 14 V. It is shown that the cells have very uniform distribution of both programmed and erased threshold voltage. It is also shown that the cell endures up to half million cycling tests.     

Fabrication and numerical simulation of the permeable base transistor

A new transistor structure has been reported in which a thin tungsten grating has been embedded inside a single crystal of gallium arsenide. The embedded metal grating, which forms a Schottky barrier with the gallium arsenide, is the base of the transistor and can be used to raise and lower a potential barrier in the semiconductor between the grating lines. The name given to this device is the permeable base transistor (PBT). Devices have been fabricated with a noise figure of 3.5 dB, an associated gain of 9 dB at 4 GHz, and a maximum frequency of oscillation of 17 GHz. This transistor structure is numerically modeled over a wide range of metal grating thicknesses, periodicities, and carrier concentrations. The results from these simulations have been condensed into a unified equation for the base-to-collector transfer characteristic which is valid for the PBT, FET's, and bipolar transistors, and simplifies the comparison between different device structures. A new iterative technique has been used to approximate the nonequilibrium electron velocity, leading to a predicted fTabove 200 GHz, a maximum frequency of oscillation near 1000 GHz and a power-delay product below 1 fJ for devices with small grating dimensions and large carder concentrations.     

Fabrication of asymmetric Ge Schottky tunneling source n-channel field-effect transistor and its characterization of tunneling conduction

An asymmetric Schottky tunneling source field-effect transistor (STS FET) is a prospective device structure to suppress the short channel effect and to reduce the off-state current. An obstacle to implement a STS FET with a high mobility Ge channel was to form a metal/Ge contact with a low electron barrier height (Φ_BN). Recently, we succeeded in the fabrication of a TiN/Ge contact with an extremely low Φ_BN. In this study, a Ge-STS n-channel FET was fabricated, here PtGe/Ge and TiN/Ge contacts were used as the source and the drain. The device showed well-behaved transistor operation. From the current-voltage measurements in the wide temperature range of 160–300 K, the conduction mechanism from the source to the channel is confirmed to be field emission tunneling. This result will be the first step toward achieving a high-performance Ge-STS n-FET.     

Fabrication and operation of a velocity modulation transistor

The velocity modulation transistor (VMT) has two channels with differing velocities. Small vertical distances between these channels can be achieved using epitaxial growth, opening the opportunity for higher speed than the high electron mobility transistor (HEMT). Experimental results from a VMT realized using the AlGaAs/GaAs system are given. The VMT channel carrier population as a function of input gate voltage is calculated for HEMTs and VMTs using a one-dimensional (1-D) numerical model. This supports a proposed equivalent circuit model for the VMT, which is used to compare VMT performance to that of HEMTs. A noise model for the VMT is developed, and this model suggests that HEMT-like noise is achievable with good carrier confinement. The dual gate, dual-channel VMT, while more complex than the HEMT, may be useful in applications such as analog-to-digital converters (ADCs) and microwave amplifiers     

纳米结构制备及硅单电子晶体管的研究

介绍了用电子束光刻、反应离子刻蚀方法制备硅量子线和用电子束光刻、电子束蒸发以及剥离技术制备纳米金属栅的工艺方法;用这种工艺在p型SIMOX硅片上成功制造了一种单电子晶体管;在器件的电流电压特性上观测到明显的库仑阻塞效应和单电子隧穿效应以及在固定的Vds电压下,源漏电流(Ids)随栅极电压(Vgs)变化的一系列周期变化的电流振荡特性.     

Fabrication of horizontal current bipolar transistor (HCBT)

The fabrication and characterization of very compact horizontal current bipolar transistor (HCBT) is presented. The active transistor region is processed in the sidewalls of the n-hill, which makes this structure attractive for the integration with pillar-like CMOS with minimum process additions. HCBT technology is simple with 5 lithography masks. The active n-hills are isolated by newly developed chemical-mechanical planarization (CMP) and etch back of oxide. The <110> substrate is used for HCBT fabrication utilizing <111> crystal planes as the active sidewalls. This enables the use of crystallographic dependent etchants for the minimization of the sidewall roughness and dry etching defects, as well as increases the controllability and repeatability of intrinsic transistor doping process. The active transistor regions are processed by angled ion implantation in self-aligned manner. The processed structures result in a cutoff frequency-breakdown voltage (f/sub T/BV/sub CEO/) product of 69.5 GHzV and current gain-Early voltage (/spl beta/V/sub A/) of 4800 V. The high-frequency characteristics are limited by the wide extrinsic base due to the coarse lithography resolution used for fabrication. It is shown by simulations that the improvement of (f/sub T/) and maximum oscillation frequency (f/sub max/) up to 24 and 50 GHz, respectively, can be achieved with finer lithography employed.     

Fabrication of widegap-emitter Schottky-collector transistor using GaInAs/InP

A widegap-emitter transistor with a Schottky collector has been fabricated using n-InP as the emitter, p-GaInAs as the base layer and Ni as the Schottky metallisation. The fabricated transistors show a current gain better than 5 in the common-emitter configuration.     

Design and characterization of a step-recovery switching transistor

Fast rise time pulses can be generated with a special high-frequency silicon transistor structure having a collector impurity profile designed to control charge storage in the collector. When switched out of saturation it operates in a manner analogous to a step-recovery diode. The theory of operation is discussed along with the design and fabrication of the diffused impurity profiles. Its unique geometry combines planar and mesa technologies. Experimental transistors have a storage time of approximately 2-30 ns followed by a fall time as fast as 0.5 ns. The storage time can be adjusted by varying the initial base current or the driving pulse. The storage time and fall time are accurately characterized by the charge-control model. A transformer input circuit gives the best switching performance. Control devices of conventional planar structure fail to produce fast switching times. They demonstrate the failure of the charge-control model in describing the fall time of planar transistors in general.     

On modelling and characterization of single electron transistor

As the nanotechnology rose to the surface, single electron transistor (SET) was invented. In contrast to the well-known response of MOS current, SET current has peaks at certain gate voltages, which disappears at other gate voltages. The SET has promised to be valuable in many applications for its high speed and low power consumption. First, a comparison was drawn between different models of SET based on the orthodox theory. Such theory explains electron transport from source to drain, employing free energies, tunnel rates and coulomb blockade phenomenon, in addition to quantizing electron tunnelling. Afterwards, a simplified model was proposed to account for unnecessary lengthy calculation processes, resulting from the large number of states assumed for simulation. The proposed PSPICE simplified model was confirmed by comparing its results to the results of the available models, and it was found to agree well with them. Taking much less runtime than the available models, the proposed model can easily be used to simulate SET-based integrated circuits on PSPICE.     

Fabrication and characterization of NEMS

We proposed a called“nano-fabrication based on MEMS technology”approach to realize the typical nano-electro- mechanical structures,such as integrated nano probe,ultrathin cantilever,silicon nano wire,and doubly clamped nano beam, to demonstrate the feasibility and advantages.We also introduced the characterization of nano structures based on laser vibrometer and piezoresistive effect,the latter method was first time applied to investigate a doubly daped nanobeam with a thickness of about 200 nm.     

Fabrication technique for Si single-electron transistor operatingat room temperature

A Si single electron transistor (SET) was fabricated by converting a one-dimensional Si wire on a SIMOX substrate into a small Si island with a tunnelling barrier at each end by means of pattern-dependent oxidation. With this structure, the total capacitance was reduced to ~2aF, which enabled conductance oscillation of the SET at room temperature     

Fabrication of raised S/D gate-all-around transistor and gate misalignment analysis

In this letter, we present the implementation of a new raised source/drain (S/D) gate-all-around transistor (GAT). The device is fabricated on a bulk silicon wafer using a technique known as metal-induced-lateral-crystallization (MILC). Compared to conventional single gate MOSFETs, the GAT shows a smaller subthreshold-slope (SS), reduced drain-induced barrier lowering (DIBL), and almost doubled (187%) drive current. Gate misalignment is briefly studied using this novel device. It is found that the SS, DIBL, and drive current will degrade abruptly when gate misalignment is larger than 17% of gate length.     

Fabrication of a low-noise beam-leaded microwave bipolar transistor by electron- and photolithography

A low-noise beam-leaded microwave bipolar transistor was fabricated with a combination of electron- and photolithography. Four of the eleven levels which were related to the patterning of the active region were patterned directly on the silicon wafers by the Bell Laboratories Electron Beam Exposure System (EBES). The registration tolerance of the 1-µm emitter stripes to the thin-gold metallization fingers was ± ¼-µm. This was routinely achieved on the 2-in wafers for all the levels written on EBES. The device processing employed a modified self-aligned emitter process which allows very highly doped inactive base and emitters without the problem of soft emitter-base junction. RF measurements of typical transistors show a minimum noise figure of 1.8 dB and an available gain of 12 dB at 1.7 GHz.     

Computer-aided transistor design, characterization, and optimization

A systematic and general method of computing ac and dc characteristics of double-diffused junction transistors using major process parameters such as dimensions of the device, surface concentration, junction depth, diffusion time, temperature, and diffusion coefficient as a function of temperature and impurity concentration is described. These parameters can be checked during the process and, therefore, can aid the process control problem by predicting the expected values of junction depth and sheet resistivity. If the specified control parameters are met during the fabrication, the ac and dc characteristics of the device will be realized. The time and/or frequency response of a circuit can be computed using the ac and dc characteristics of the diffused devices of the circuit on the basis of a distributed or an equivalent lumped model. The measurement of important ac parameters on the basis of these models has also been simulated on the computer, thus aiding the characterization problem of the device in the integrated circuit environment. Also, the switching speed of a loaded logic net can be computed and optimized by trading off interacting parameters and relating them back to the original diffusion process parameters and dimensions of the components. Finally, experimental verification of the computed results has been accomplished and found to be satisfactory.     

Theoretical and experimental characterization of the DUal-BAse transistor (DUBAT)

A new A-type integrated voltage controlled differential negative resistance device using an extra effective base region to form a lateral pnp (npn) bipolar transistor beside the original base region of a vertical npn (pnp) bipolar junction transistor, and so called the DUal BAse Transistor (DUBAT), is studied both experimentally and theoretically, The DUBAT has three terminals and is fully comparible with the existing bipolar integrated circuits technologies. Based upon the equivalent circuit of the DUBAT, a simple first-order analytical theory is developed, and important device parameters, such as: the I–V characteristic, the differential negative resistance, and the peak and valley points, are also characterized. One of the proposed integrated structures of the DUBAT, which is similar in structure to I²L but with similar high density and a normally operated vertical npn transistor, has been successfully fabricated and studied. Comparisons between the experimental data and theoretical analyses are made, and show in satisfactory agreements.     

铁电微管的制备与表征

采用化学浸润法在多孔硅模板上制备了锆钛酸铅(PbZr0.52Ti0.48O3,PZT)铁电微管,X射线衍射分析表明铁电微管为钙钛矿结构.运用扫描电子显微镜和原子力显微镜对铁电微管的微现形貌进行了观察,其姑果显示两种方法所测得的铁电微管直径不同.利用压电响应力显微镜观察到了铁电微管的电畴图像,并测得了铁电微管的微区电滞回...