Electromigration lifetime improvement of copper interconnect by cap/dielectric interface treatment and geometrical design

A significant improvement of electromigration (EM) lifetime is achieved by modification of the preclean step before cap-layer deposition and by changing Cu cap/dielectric materials. A possible mechanism for EM lifetime enhancement was proposed. Cu-silicide formation prior to cap-layer deposition and adhesion of Cu/cap interface were found to be the critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to electromigration median-time-to-failure and activation energy. Effects of layout geometrical variation and stress current direction were also investigated.     

A copper-dielectric cap interface with high resistance to electromigration for high performance semiconductor devices

In highly integrated semiconductor devices the time to failure of copper interconnects strongly depends on the properties of the copper-dielectric cap interface. In this work a production capable preparation of copper-dielectric cap interfaces with a high resistance to electromigration (EM) has been developed for 90 and 65 nm dual damascene technologies. With a new soft silicidation pretreatment of the copper metallization followed by a deposition of a SiCN or SiN cap the EM lifetime could be improved 3.5× referring to a standard SiCN capping process. The new pretreatment enables the formation of an epitaxial copper silicide layer on top of the copper metal lines which is seen as the key factor of the lifetime improvement. The new kind of cap layer process enables the lifetime improvement with only negligible increase of metal sheet resistance. The surface damage of copper and the low k inter-level dielectric which is typically caused during the copper precleaning could be minimized significantly. It is shown that there is no linear correlation between adhesion to copper and electromigration performance.     

Effect of low k dielectrics on electromigration reliability for Cu interconnects

Multi-link statistical test structures were used to study the effect of low k dielectrics on EM reliability of Cu interconnects. Experiments were performed on dual-damascene Cu interconnects integrated with oxide, CVD low k, porous MSQ, and organic polymer ILD. The EM activation energy for Cu structures was found to be between 0.8 and 1.0 eV, indicating mass transport dominated by diffusion at the Cu/SiN_x cap-layer interface, independent of ILD. Compared with oxide, the decrease in lifetime and (jL)_c observed for low-k structures can be attributed to less dielectric confinement in the low k structures. An effective modulus B obtained by finite element analysis was used to account for the dielectric confinement effect on EM and found to correlate well with EM lifetime and the (jL)_c product of low-k interconnects.     

具有冗余设计的铜互连线电迁移可靠性评估

铜互连的电迁移可靠性与晶粒结构、几何结构、制造工艺以及介质材料等因素有着密切的关系。分别试制了末端有一定延伸的互连线冗余结构设计的样品,以及无冗余结构的互连线样品,并对样品进行了失效加速测试。测试结果显示,采用冗余结构设计的互连线失效时间更长,具有更好的抗电迁移可靠性。对冗余结构的失效模式进行了讨论,并结合互连线的制造工艺,指出采用冗余结构设计的互连线可以在有效改善互连线的电迁移特性,而且不会引入其他影响可靠性的因素,是一种有效提高铜互连电迁移可靠性的方法。     

Copper-dielectric cap interface with enhanced reliability for 45 nm technology and beyond

A production capable preparation of a Cu-dielectric cap interface with a significantly enhanced reliability robustness has been developed for the 45 nm dual damascene technology and beyond. The electromigration (EM) lifetime could be improved by a factor of 2 with an advanced in situ cleaning process (ACP) including a soft silicidation step of the Cu metallization prior to the Cu-cap deposition. The increase of the Cu metal line resistivity can be controlled and limited to <6%. Anneal experiments at high temperature underline a high thermal stability of the Cu-cap interface including the copper-silicide (CuSi) intralayer. The new ACP is applicable to Cu interconnects built with dense or porous ultra-low-k (ULK) dielectrics because the process minimizes the surface damage. This yields in a doubled dielectric breakdown strength of a Cu damascene structure with a ULK inter-level dielectric by implementation of the ACP.     

A Model for Understanding Electromigration-Induced Void Evolution in Dual-Inlaid Cu Interconnect Structures

Electromigration-induced void evolution in various dual-inlaid copper (Cu) interconnect structures was simulated by applying a phenomenological model assisted by Monte Carlo-based simulations, considering the redistribution of heterogeneously nucleated voids and/or pre-existing vacancy clusters at the Cu/dielectric cap interface during electromigration. The results indicate that this model can qualitatively explain the electromigration-induced void evolution observed during experimental in situ secondary-electron microscopy (SEM) investigations as well as in various other reported studies. The electromigration mechanism in Cu interconnect structures and differences in the peculiar electromigration-induced void evolution in various dual-inlaid Cu interconnect structures can be clearly understood based on this model. These findings warrant reinvestigation of technologically important electromigration mechanisms by developing rigorous models based on similar concepts.     

铜互连电迁移可靠性的研究进展

综述了近年来铜互连电迁移可靠性的研究进展;讨论了电迁移的基本原理、常用研究方法及主要失效机制;探讨了改善铜互连电迁移性能的各种方法,如铜合金、增加金属覆盖层及等离子体表面处理。最后,指出了铜互连可靠性研究中存在的问题。     

Highly reliable copper dual-damascene interconnects with self-formed MnSi/sub x/O/sub y/ barrier Layer

Copper (Cu) dual-damascene interconnects with a self-formed MnSi/sub x/O/sub y/ barrier layer were successfully fabricated. Transmission electron microscopy shows that approximately 2-nm thick and continuous MnSi/sub x/O/sub y/ layer was formed at the interface of Cu and dielectric SiO/sub 2/, and that no barrier was formed at the via bottom because no oxygen was at the via bottom during annealing. No leakage-current increase was observed, and electron energy loss analysis shows that no Cu was in SiO/sub 2/, suggesting that MnSi/sub x/O/sub y/ layer has sufficient barrier properties for Cu, and that the concept of self-forming barrier process works in Cu dual-damascene interconnects. Via chain yield of more than 90% and 50% reduction in via resistance were obtained as compared with physical vapor deposited tantalum barrier, because there is no barrier at the via bottom. In addition, no failure in the stress-induced voiding measurement was found even after a 1600-h testing. No failure in electromigration (EM) testing was found, as the electron flow is from the lower level interconnects through via up to upper level interconnects even after 1000-h testing. At least, four times EM lifetime improvement was obtained in the case of electron flow from upper level interconnect through via down to lower level interconnects. Significant EM lifetime improvement is due to no flux divergence site at the via bottom, resulting from there being no bottom barrier at the via.     

ULSI中Cu互连线的显微结构及可靠性

观察了ULSI中大马士革结构的Cu互连线的晶粒生长和晶体学取向.分析了线宽及退火对Cu互连线显微结构及电徙动的影响.Cu互连线的晶粒尺寸随着线宽的变窄而减小.与平坦Cu膜相比,Cu互连线形成微小的晶粒和较弱的 (111) 织构.300℃、30min退火促使Cu互连线的晶粒长大、(111) 织构发展,从而提高了Cu互连线抗电徙动的能力.结果表明,Cu的扩散涉及晶界扩散与界面扩散,而对于较窄线宽的Cu互连线,界面扩散成为Cu互连线电徙动失效的主要扩散途径.     

Reliability and early failure in Cu/oxide dual-damascene interconnects

Recent results on up-direction electromigration (EM) studies on Cu dual-damascene (DD) interconnects are presented. The issue of the DD process and its potential effect on EM reliability is described with special focus on the peculiarities of the DD interconnect architecture in comparison to the previous subtractively etched Al-based interconnect technology. Experiments performed on multilink, DD interconnects that highlight EM reliability issues, such as early failure, and the Blech effect are summarized.     

An introduction to Cu electromigration

Electromigration is a major reliability concern in today’s integrated circuits due to the aggressive scaling of interconnect dimensions and the ever-increasing current densities at operation. In addition, the recent introduction of new materials and processing schemes lead to even more challenges in guaranteeing interconnect robustness against electromigration failure. In this article, we review basic electromigration physics in which the main differences between Al- and Cu-based interconnects relevant to electromigration are covered. We also discuss recent process-related advances in electromigration reliability such as the use of alloys and metal caps. Next, the impact of low-k inter-level dielectrics (ILD) on electromigration performance is addressed. Finally, the methodology of electromigration lifetime extrapolation, including reliability assessments of more complex interconnect geometries, is covered.     

Electromigration failure in ultra-fine copper interconnects

This paper presents experimental evidence suggesting that electromigration (EM) can be a serious reliability threat when the dimension of Cu interconnects approaches the nanoscale range. To understand the failure mechanism prevailing in nanoscale Cu interconnects, single-level, 400-μm long interconnects with various effective widths, ranging from 750 nm to 80 nm, were made, EM tested, and characterized in this investigation. The results indicate that interface EM (Cu/barrier) may be the predominant EM mechanism in all line widths. The evidence supporting the active Cu/barrier interface EM includes the fact that the EM lifetime is inversely proportional to the interface area fraction. Microscopic analysis of the failure sites also supports the conclusion of interface EM because voids and hillocks are found at the ends of the test strip, which is not possible if lines fail by grain-boundary EM in the test structure used in this study. In addition, our study finds evidence that failure is assisted by a secondary mechanism. The influence of this factor is particularly significant when the feature size is small, resulting in more uniform distribution of failure time in narrower lines. Although limited, evidence suggests that the secondary factor is probably attributed to pre-existing defects or grain boundaries.     

Electromigration characteristics in dual-damascene copper interconnects by difference of via structures

In order to improve the interconnect performance, copper has been used as the interconnect material instead of aluminum. One of the advantages of using copper interconnects instead of aluminum is better electromigration (EM) performance and lower resistance for ultralarge-scale integrated (ULSI) circuits. Dual-damascene processes use different approaches at the via bottom for lowering the via resistance. In this study, the effect of a Ta/TaN diffusion barrier on the reliability and on the electrical performance of copper dual-damascene interconnects was investigated. A higher EM performance in copper dual-damascene structures was obtained in barrier contact via (BCV) interconnect structures with a Ta/TaN barrier layer, while a lower EM performance was observed in direct contact via (DCV) interconnect structures with a bottomless process, although DCV structures had lower via resistance compared to BCV structures. The EM failures in BCV interconnect structures were formed at the via, while those in DCV interconnect structures were formed in the copper line. The existence of a barrier layer at the via bottom was related to the difference of EM failure modes. It was confirmed that the difference in EM characteristics was explained to be due to the fact that the barrier layer at the via bottom enhanced the back stress in the copper line.     

A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections

Integration of Cu with low k dielectrics has gained wide acceptance for 130 nm and beyond technology nodes at back-end-of-line (BEOL) interconnection in order to reduce both the RC delay and parasitic capacitance. Wet clean is one of the critical steps to remove post plasma etch residues. In this paper, the impacts of wet clean process after etching of (a) via, (b) metal 2 trench and (c) Cu cap of dual damascene structure on electrical performance of 130 nm Cu/CVD low k SiOCH metallization were explored and discussed. Electrical yields and dielectric breakdown strength of interconnects from the use of batch spray and single wafer processing systems of wet clean were also compared. We observed that electrical yields of interconnects were considerably dependant on optimized processing conditions (temperature, time, and mega-sonic power) and appropriate wet clean chemistry. The use of fluoride-based mixture of wet clean chemical for all three post-etch clean is very effective in cleaning the via and trench line before Ta barrier/Cu seed deposition. As a result, we successfully integrated double level Cu/CVD low k BEOL interconnection with excellent electrical and reliability performance.     

Reliability challenges for copper interconnects

In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low-k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.     

Applications of finite element methods for reliability study of ULSI interconnections

Three main failure mechanisms of ULSI interconnects are the electromigration (EM), stress induced voiding (SIV) and low-k dielectric breakdown. Reliability tests for these mechanisms are too long to meet the development time requirement, and the underlying dominant mechanisms cannot be identified, rendering difficulty in design-in reliability for integrated circuit. Facing the challenges in the reliability study of the interconnect system, physics based simulation and modeling is found to be essential, and finite element method (FEM) is a suitable tool. A few examples on the application of FEM to study the degradation processes and identification of potential failure sites in interconnects due to EM and SIV are given here. The study of the process induced degradation of the effective k value of low-k dielectric in ULSI interconnect system using FEM is also presented.     

Effects of material interfaces in Cu/low-/spl kappa/ damascene interconnects on their performance and reliability

The performance and reliability of Cu/Low-/spl kappa/ damascene interconnects are investigated from the view point of the material interface structure. We are focusing especially on the heterointerfaces between the Cu and the barrier metal (BM), as well as between the hard mask (HM) and the capping barrier dielectrics (CAP) covered on the Cu interconnects. It is found that the highest via reliabilities of electromigration (EM) and thermal cycle are established by the barrier-metal-free (BMF) structure without the heterointerface between the Cu and the BM due to the strong Cu-to-Cu connection at the via bottom. The interline time-dependant dielectric breakdown lifetime is improved mostly by using a HM with the same materials as the CAP layer, referred to as an unified structure, which diminishes the heterointerface between the HM and the CAP. These ideal structures without the material heterointerfaces derive the highest reliability and performance. Structural control of the material heterointerfaces in the actual Cu/low-/spl kappa/ damascene interconnect is crucial for the high reliability and performance.     

A numerical procedure for simulating delamination growth on interfaces of interconnect structures

A fracture mechanics based numerical approach is developed for modeling delamination growth on materials interfaces in integrated circuit (IC) interconnects. In this approach, the heterogeneous interconnect structures neighboring the cracked interface are approximated by homogenized layers with transversely isotropic elastic properties. Evolution of the interface crack under fatigue condition is modeled by using an incremental approach, in which the fracture mechanics parameters including the strain energy release rate, the normalized stress intensity factors and phase angles are first estimated by post-processing finite element solutions. The fracture mechanics parameters along the curvilinear front of the interface crack are then substituted into a steady-state fatigue crack growth model for obtaining the crack growth increments. The process is repeated to simulate subsequent crack growth for predicting interconnect structural reliability under fatigue condition. The evolution of an interface corner crack in a back-end-of-line (BEOL) Cu/low-k interconnect structure under temperature cycling condition is considered as an application example of the procedure.     

Electromigration lifetimes and void growth at low cumulative failure probability

We have investigated electromigration (EM) lifetimes and void formation at cumulative failure probability of around 50 ppm. We carried out EM test in damascene Cu lines using sudden-death test structures. Cumulative failure probability of the test ranges from 50 ppm to 90%. To investigate the void nucleation and growth behaviour, Cu microstructures were investigated by using scanning transmission electron microscopy (S-TEM) and electron backscatter diffraction (EBSD) technique. EM lifetime shows strong correlation with the void nucleation site and the void volume. In addition, the worst case for EM lifetime is that wide angle grain boundary exists just under the via as a void nucleation site.