Simulation of coupled interconnects using waveform relaxation and transverse partitioning

The large number of coupled lines in an interconnect structure is a serious limiting factor in simulating high-speed circuits. A new method is presented for efficient simulation of large interconnects based on transverse partitioning and waveform relaxation techniques. The computational cost of the proposed algorithm grows linearly with the number of coupled lines. In addition, the algorithm is highly suitable for parallel implementation leading to further significant reduction in the computational complexity.     

Waveform Relaxation Techniques for Simulation of Coupled Interconnects With Frequency-Dependent Parameters

The large number of coupled lines in an interconnect structure is a serious limiting factor in simulating high-speed circuits. Waveform relaxation based on transverse partitioning has been previously presented to address this problem for interconnects with constant per-unit-length parameters. This paper extends the waveform relaxation technique to handle the more difficult and important case of frequency-dependent parameters. The computational cost of the proposed algorithm grows linearly with the number of coupled lines     

Analysis of high-speed interconnects in the presence ofelectromagnetic interference

This paper describes an efficient algorithm based on moment-matching techniques for simulation of high-speed circuits in the presence of electromagnetic interference (EMI). The proposed method is based on the recently developed complex frequency hopping (CFH) technique for interconnect analysis. The new technique is useful for susceptibility analysis and is two to three orders of magnitude faster than conventional simulation techniques. In addition, it can be extended to the analysis of interconnects with frequency-dependent parameters and nonlinear terminations     

FDTD modeling incorporating a two-port network for I/O line EMIfiltering design

Electromagnetic interference (EMI) filters are often utilized on I/O lines to reduce high-frequency noise from being conducted off the printed circuit board (PCB) and causing EMI problems. The filtering performance is often compromised at high frequencies due to parasitics associated with the filter itself, or the PCB layout and interconnects. Finite difference time domain (FDTD) modeling can be used to quantify the effect of PCB layout and interconnects, as well as filter type, on the EMI performance of I/O line filtering. FDTD modeling of a T-type and π-type filter consisting of surface-mount ferrites and capacitors is considered herein. The FDTD method is applied to model PCB layout and interconnect features, as well as the lumped element components, including the nonlinear characteristics of ferrite surface-mount parts. The EMI filters with ferrites; are included in the modeling by incorporating the time-domain Y-parameters of the two-port network into the FDTD time-marching equations. Good agreement between the FDTD modeling and S-parameter measurements supports the new FDTD algorithm for incorporating two-port networks     

Circuit analysis of electromagnetic radiation and field couplingeffects for networks with embedded full-wave modules

With continually increasing operating frequencies, the analysis of electromagnetic interference (EMI)-related effects is becoming an important issue for high-speed designs. An algorithm is presented for fast analysis of radiation and incident field coupling effects in high-speed circuits. The proposed technique provides an efficient means for combining the solutions from full-wave field solvers such as the finite-difference time-domain (FDTD) method with circuit level simulators such as SPICE for calculating radiated/coupled fields in arbitrarily shaped interconnect structures. The technique speeds up the whole simulation process by employing a model-reduction-based approach, and also overcomes the numerical stability problems associated with the FDTD, in the presence of nonlinear terminations. In addition, the proposed algorithm provides a direct access to existing vast device libraries of SPICE in EMI analysis     

Minimization of delay and crosstalk in high-speed VLSIinterconnects

Design optimization of time responses of high-speed VLSI interconnects modeled by distributed coupled transmission line networks is presented. The problem of simultaneous minimization of crosstalk, delay and reflection is formulated into minimax optimization. Design variables include physical/geometrical parameters of the interconnects and parameters in terminating/matching networks. A recently published simulation and sensitivity analysis technique for multiconductor transmission lines is expanded to directly address the VLSI interconnect environment. The new approach permits efficient physical/geometrical oriented interconnect design using exact gradient based minimax optimization. Examples of interconnect optimization demonstrate significant reductions of crosstalk, delay, distortion and reflection at all vital connection ports. The technique developed is an important step towards optimal design of circuit interconnects for high-speed digital computers and communication systems     

Broadband, electrically long vertical waveguide interconnect

A bandwidth optimised vertical interconnect using a rectangular waveguide to couple two microstrip lines is presented. The electrically long interconnect gives low insertion loss and large bandwidth, in contrast to other indirectly and directly coupled interconnects. Experimental results show <1.5 dB insertion loss and <20 dB return loss over a wide bandwidth 8.1-0.7 GHz     

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.     

Analysis of high-speed interconnects using efficient multipointPade approximation

An efficient method is presented for analysis of large interconnect circuits including lossy coupled transmission lines. Based on multipoint Pade approximations and a new expansion point search algorithm, the method can obtain single close-form frequency-domain and transient solutions of the interconnect problem with a minimum of frequency expansion points     

Characteristic analysis of coupled HTS interconnects withtwo-dimensional FDTD

In this work, the frequency-dependent RLGC parameters of high-speed coupled high T_c superconductor (HTS) interconnects are extracted with a two-dimensional (2-D) FDTD algorithm. The response signals of an HTS interconnect circuit and a normal Al interconnect circuit are simulated and compared, showing that not only the signal dispersion, delay, and magnitude decay of HTS interconnects are smaller than that of Al interconnects, the crosstalk of HTS interconnects is much smaller, too     

Analytical Model for Optimum Signal Integrity in PCB Interconnects Using Ground Tracks

In this paper, we present analytical models for line impedance and the coupling coefficient in the presence of additional ground tracks. We use a variational analysis combined with the transverse transmission-line technique to model interconnect lines guarded by ground tracks. Using the proposed model, it would be possible for designers to reduce crosstalk in coupled lines and obtain desired line impedance, thereby ensuring optimum signal integrity. The results obtained are verified by full-wave simulations and measurements performed on a vector network analyzer. The proposed model may find applications in the design and analysis of high-speed interconnects.      

Transient Simulation of Lossy Interconnects Based on a Dispersive Hybrid Phase-Pole Macromodel

A transient simulator for interconnect structures that are modeled by lossy transmission lines is outlined in this paper. Since frequency-dependent RLGC parameters must be employed to correctly model skin effects and dielectric losses for high-performance interconnects, we first study the behaviors of various lossy interconnects that are characterized by frequency-dependent line parameters (FDLPs). We then developed a frequency-domain dispersive hybrid phase-pole macromodel (DHPPM) for such lines, which consists of a constant RLGC propagation function multiplied by a residue series. The basic idea is to first extract the dominant physical phenomenology by using a propagation function in the frequency domain that is modeled by frequency-independent line parameters (FILPs). A rational function approximation is then used to account for the remaining effects of FDLP lines. By using a partial fraction expansion and analytically evaluating the required inverse Fourier transform integrals, the time-domain DHPPM can be decomposed as a sum of canonical transient responses for lines with FILP for various excitations (e.g., trapezoidal and unit step). These canonical transient responses are then expressed analytically as closed-form expressions involving incomplete Lipshitz-Hankel integrals of the first kind and Bessel functions. The closed-form expressions for these canonical responses are validated by comparing with simulation results from commercial tools like HSPICE. The DHPPM simulator can simulate transient results for various input waveforms on both single and coupled interconnect structures. Comparisons between the DHPPM results and the results produced by commercial simulation tools like HSPICE and a numerical inverse fast Fourier transform show that the DHPPM results are very accurate.     

SPICE compatible modelling of on-chip coupled interconnects

On-chip coupled interconnect lines are modelled using measured S-parameters. The physical consistency between single and coupled line model parameters are maintained in the proposed methodology. The SPICE compatible model is validated in both the frequency and the time domain using copper and ultra low-kappa coupled interconnects.     

Coupling and crosstalk between high speed interconnects inultralarge scale integrated circuits

The advent of sophisticated lithographic techniques has made it possible to fabricate densely packed ultra-large-scale-integrated (ULSI) circuits. In these chips, interconnect lines are so narrow and spaced in such close proximity that signal from one line could easily get coupled to another, causing interference and crosstalk. A general theory to model coupling between optical interconnects (waveguides) and quantum-mechanical coupling between narrow and very closely spaced silicide interconnects embedded in dielectrics (SiO₂) is presented     

Hierarchical Krylov subspace based reduction of large interconnects

In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and the Krylov subspace projection-based model order reduction methods. The new approach, called hiePrimor, first partitions a large interconnect circuit into a number of smaller subcircuits and then performs the projection-based model order reduction on each of subcircuits in isolation and on the top-level circuit thereafter. The new approach is very amenable for exploiting the multi-core based parallel computing platforms to significantly speed up the reduction process. Theoretically we show that hiePrimor can deliver the same accuracy as the flat reduction method given the same reduction order and it can also preserve the passivity of the reduced models as well. We also show that partitioning has large impacts on the performance of hierarchical reduction and the minimum-span objective should be required to attain the best performance for hierarchical reduction. The proposed method is suitable for reducing large global interconnects like coupled bus, transmission lines, large clock nets in the post-layout stage. Experimental results demonstrate that hiePrimor can be significantly faster and more scalable than the flat projection methods like PRIMA and be order of magnitude faster than PRIMA with parallel computing without loss of accuracy. Interconnect circuits with up to 4 million nodes can be analyzed in a few minutes even in Matlab by the new method.     

S-parameter-measurement-based high-speed signal transientcharacterization of VLSI interconnects on SiO2-Si substrate

A new S-parameter-based signal transient characterization method for very large scale integrated (VLSI) interconnects is presented. The technique can provide very accurate signal integrity verification of an integrated circuit (IC) interconnect line since its S-parameters are composed of all the frequency-variant transmission line characteristics over a broad frequency band. In order to demonstrate the technique, test patterns are designed and fabricated by using a 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The time-domain signal transient characteristics for the test patterns are then examined by using the S-parameters over a 50 MHz to 20 GHz frequency range. The signal delay and the waveform distortion presented in the interconnect lines based on the proposed method are compared with the existing interconnect models. Using the experimental characterizations of the test patterns, it is shown that the silicon substrate effect and frequency-variant transmission line characteristics of IC interconnects can be very crucial     

DEPACT: delay extraction-based passive compact transmission-line macromodeling algorithm

With the continually increasing operating frequencies, signal integrity and interconnect analysis in high-speed designs is becoming increasingly important. Recently, several algorithms were proposed for macromodeling and transient analysis of distributed transmission line interconnect networks. The techniques such as method-of-characteristics (MoC) yield fast transient results for long delay lines. However, they do not guarantee the passivity of the macromodel. It has been demonstrated that preserving passivity of the macromodel is essential to guarantee a stable global transient simulation. On the other hand, methods such as matrix rational approximation (MRA) provide efficient macromodels for lossy coupled lines, while preserving the passivity. However, for long lossy delay lines this may require higher order approximations, making the macromodel inefficient. To address the above difficulties, this paper presents a new algorithm for passive and compact macromodeling of distributed transmission lines. The proposed method employs delay extraction prior to approximating the exponential stamp to generate compact macromodels, while ensuring the passivity. Validity and efficiency of the proposed algorithm is demonstrated using several benchmark examples     

Nonlinear circuit-reduction of high-speed interconnect networksusing congruent transformation techniques

A new algorithm based on Krylov subspace methods is proposed for efficient simulation of large interconnect networks with nonlinear terminations. Reduction is obtained by projecting the original system described by nonlinear differential equations into a subspace of a lower dimension. The reduced circuit can be simulated using conventional numerical integration techniques. Significant reduction in computational expense is achieved as the size of the reduced equations is much less than that of the original system. The new algorithm is potentially useful for analysis of lossy coupled transmission lines with nonlinear terminations     

Interconnect design strategy: structures, repeaters and materialswith strategic system performance analysis (S2PAL) model

In this paper, we propose a novel methodology for scheming an interconnect strategy, such as what interconnect structure should be taken, how repeaters should be inserted, and when new metal or dielectric materials should be adopted. In the methodology, the strategic system performance analysis model is newly developed as a calculation model that predicts LSI operation frequency and chip size with electrical parameters of transistors and interconnects as well as circuit configuration. The analysis with the model indicates that interconnect delay overcomes circuit block cycle time at a specific length; D_c-cross. Here tentatively, interconnects shorter than D_c-cross are called local interconnects, and interconnects longer than that as global ones. The cross-sectional structures for local and global tiers are optimized separately. We also calculate global interconnect pitch and the chip size enlarged by the global interconnect pitch and the inserted repeaters, and then estimate the effectiveness of introducing new materials for interconnects and dielectrics