OpenSourcePACS: an extensible infrastructure for medical image management.

The development of comprehensive picture archive and communication systems (PACS) has mainly been limited to proprietary developments by vendors, though a number of freely available software projects have addressed specific image management tasks. The openSourcePACS project aims to provide an open source, common foundation upon which not only can a basic PACS be readily implemented, but to also support the evolution of new PACS functionality through the development of novel imaging applications and services. openSourcePACS consists of four main software modules: 1) image order entry, which enables the ordering and tracking of structured image requisitions; 2) an agent-based image server framework that coordinates distributed image services including routing, image processing, and querying beyond the present digital image and communications in medicine (DICOM) capabilities; 3) an image viewer, supporting standard display and image manipulation tools, DICOM presentation states, and structured reporting; and 4) reporting and result dissemination, supplying web-based widgets for creating integrated reports. All components are implemented using Java to encourage cross-platform deployment. To demonstrate the usage of openSourcePACS, a preliminary application supporting primary care/specialist communication was developed and is described herein. Ultimately, the goal of openSourcePACS is to promote the wide-scale development and usage of PACS and imaging applications within academic and research communities.     

Design of a system software based on a Java SoC processor

Java technology is spreading rapidly all over the world in recent years. It is a popular application development language for its well-encapsulation, platform-independent and high security. There are great amounts of Java games and other gadgets on mobile platforms, as well as on set-up-box systems. As Java applications become more sophisticated, the Java Virtual Machine (JVM) middle-wares in embedded systems are not satisfying, Java-specific chips extend in the market. All existing Java-based system software or Operating System (OS) are used on JVM, they cannot be used on Java processors. It is important to develop a pure Java system software or OS so that embedded systems using Java processors will have great performance in Java applications. This paper presents a set of system software designed for a Java-specified processor VP6K, which is also a System-on-Chip (SoC). This system software includes real-time multitask dispatching, file management, device management, hardware drivers, and infrastructural Application Programming Interface (APIs). According to experimental results, the system software provides interfaces for Java programs to fully handle CPU resource, so that all applications can be executed properly and efficiently. VP6K embedded platform shows its good performance for Java applications when the system software is implemented.     

基于手机平台的人脸检测系统的研究

随着通信技术和图像处理技术的发展,手机不仅是一种便携的通信工具,而且能够用来拍照。针对市场上的非智能手机拍照的性能欠佳又不具备图像处理功能的缺点,选取了扩展的Haar特征,利用Intel开源的图像处理软件OpenCV在智能手机操作系统上实现了一个Adaboost人脸检测系统,描述了建立样本、图像预处理、特征提取、构造级联分类器和目标检测等过程。多次实验证明,该系统正检率高,检测时间短,具有一定的实用性。     

Image processing on high-performance RISC systems

The recent progress of RISC technology has led to the feeling that a significant percentage of image processing applications, which in the past required the use of special purpose computer architectures or of ad hoc hardware, can now be implemented in software on low cost general purpose platforms. We decided to undertake the study described in this paper to understand the extent to which this feeling corresponds to reality. We selected a set of reference RISC-based systems to represent RISC technology, and identified a set of basic image processing tasks to represent the image processing domain. We measured the performance and studied the behavior of the reference systems in the execution of the basic image processing tasks by running a number of experiments based on different program organizations. The results of these experiments are summarized in a table, which can be used by image processing application designers to evaluate whether RISC-based platforms are able to deliver the computing power required for a specific application     

Evaluating quality of compressed medical images: SNR, subjectiverating, and diagnostic accuracy

Compressing a digital image can facilitate its transmission, storage, and processing. As radiology departments become increasingly digital, the quantities of their imaging data are forcing consideration of compression in picture archiving and communication systems (PACS) and evolving teleradiology systems. Significant compression is achievable only by lossy algorithms, which do not permit the exact recovery of the original image. This loss of information renders compression and other image processing algorithms controversial because of the potential loss of quality and consequent problems regarding liability, but the technology must be considered because the alternative is delay, damage, and loss in the communication and recall of the images. How does one decide if an image is good enough for a specific application, such as diagnosis, recall, archival, or educational use? The authors describe three approaches to the measurement of medical image quality: signal-to-noise ratio (SNR), subjective rating, and diagnostic accuracy. They compare and contrast these measures in a particular application, consider in some depth recently developed methods for determining diagnostic accuracy of lossy compressed medical images and examine how good the easily obtainable distortion measures like SNR are at predicting the more expensive subjective and diagnostic ratings. The examples are of medical images compressed using predictive pruned tree-structured vector quantization, but the methods can be used for any digital image processing that produces images different from the original for evaluation     

Workflow-enabled distributed component-based information architecture for digital medical imaging enterprises

Few information systems today offer a flexible means to define and manage the automated part of radiology processes, which provide clinical imaging services for the entire healthcare organization. Even fewer of them provide a coherent architecture that can easily cope with heterogeneity and inevitable local adaptation of applications and can integrate clinical and administrative information to aid better clinical, operational, and business decisions. We describe an innovative enterprise architecture of image information management systems to fill the needs. Such a system is based on the interplay of production workflow management, distributed object computing, Java and Web techniques, and in-depth domain knowledge in radiology operations. Our design adapts the approach of "4+1" architectural view. In this new architecture, PACS and RIS become one while the user interaction can be automated by customized workflow process. Clinical service applications are implemented as active components. They can be reasonably substituted by applications of local adaptations and can be multiplied for fault tolerance and load balancing. Furthermore, the workflow-enabled digital radiology system would provide powerful query and statistical functions for managing resources and improving productivity. This paper will potentially lead to a new direction of image information management. We illustrate the innovative design with examples taken from an implemented system.     

Hardware-accelerated design space exploration framework for communication systems

The efficient hardware implementation of signal processing algorithms requires a rigid characterization of the interdependencies between system parameters and hardware costs. Pure software simulation of bit-true implementations of algorithms with high computational complexity is prohibitive because of the excessive runtime. Therefore, we present a field-programmable gate array (FPGA) based hybrid hardware-in-the-loop design space exploration (DSE) framework combining high-level tools (e.g. MATLAB, C++) with a System-on-Chip (SoC) template mapped on FPGA-based emulation systems. This combination significantly accelerates the design process and characterization of highly optimized hardware modules. Furthermore, the approach helps to quantify the interdependencies between system parameters and hardware costs. The achievable emulation speedup using bit-true hardware modules is a key enabling the optimization of complex signal processing systems using Monte Carlo approaches which are infeasible for pure software simulation due to the large required stimuli sets. The framework supports a divide-and-conquer approach through a flexible partitioning of complex algorithms across the system resources on different layers of abstraction. This facilitates to efficiently split the design process among different teams. The presented framework comprises a generic state of the art SoC infrastructure template, a transparent communication layer including MATLAB and hardware interfaces, module wrappers and DSE facilities. The hardware template is synthesizable for a variety of FPGA-based platforms. Implementation and DSE results for two case studies from the different application fields of synthetic aperture radar image processing and interference alignment in communication systems are presented.     

Applications of VLSI circuits to medical imaging

The application of advanced VLSI circuits to medical imaging is explored. The relationship of both general-purpose signal processing chips and custom devices to medical imaging is discussed using examples of fabricated chips. In addition, advanced-aided design tools for silicon compilation are presented. Particular attention is given to the application of VLSI circuits to 3-D image display with ultrasound systems. It is concluded that devices built with these tools represents a possible alternative to custom devices and general-purpose signal processors for the next generation of medical imaging systems     

Designing Run-Time Reconfigurable Systems with JHDL

Run-time reconfigurable (RTR) systems are FPGA-based systems that reconfigure FPGAs during execution to alter hardware organization and composition to meet the varying needs of applications as they execute. These systems are difficult to describe with conventional tools (schematic capture, VHDL synthesis, etc.) because most tools assume that the underlying hardware organization is static. JHDL is a Java-based design environment capable of describing, netlisting, simulating and executing complex, dynamic RTR systems. Using conventional Java syntax, users describe hardware structures as objects; as these hardware-object constructors are invoked, JHDL automatically configures hardware circuits onto FPGA hardware, thus directly supporting the dynamic nature of RTR systems with standard language constructs. JHDL also supports codesign of the software and hardware parts of the system; in other words, the entire application can be described in a single piece of Java code that can be co-simulated/co-executed with the FPGA hardware. To date, RTR design with JHDL has focused on the development of automated target recognition (ATR) systems, and working systems described in JHDL have been demonstrated.     

SoC Memory Hierarchy Derivation from Dataflow Graphs

Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation and how these memory architectures can be mapped to a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and by creating memory hierarchies, off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm, with a minimal increase in memory size. This analysis is verified using results gathered from implementation of the motion estimation algorithm on a Xilinx Virtex-4 FPGA, where the delay between the memories and processing elements drops from 14.2 ns down to 1.878 ns through the refinement of the memory architecture. Care must be taken when modeling these algorithms however, as inefficiencies in these models can be easily translated into overuse of hardware resources.     

Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management

MATISSE is a design environment intended for developing systems characterized by a tight interaction between control and data-flow behavior, intensive data storage and transfer, and stringent real-time requirements. Matisse bridges the gap from a system specification, using a concurrent object-oriented language, to an optimized embedded single-chip hardware/software implementation. Matisse supports stepwise exploration and refinement of dynamic memory management, memory architecture exploration, and gradual incorporation of timing constraints before going to traditional tools for hardware synthesis, software compilation, and inter-processor communication synthesis. With this approach, specifications of embedded systems can be written in a high-level programming language using data abstraction. Application of MATISSE on telecom protocol processing systems in the ATM area shows significant improvements in area usage and power consumption.     

计算和存储空间受限下的数据稀疏核分析方法

针对核主成分分析算法广泛面临的训练样本数量大而带来的计算和存储空间的问题,提出了基于1类支持向量理论的稀疏核主成分分析算法,该方法适合于计算和存储空间受限下的应用场合,如小型硬件平台下的图像检索系统、医学辅助诊断系统等.通过求解最优方程找到能够代表原始样本空间的少量典型样本,这些样本作为计算核数据矩阵,大大节省了核矩阵计算的时间和存储空间成本,在有限的训练样本集上最大限度在硬件平台下图像处理领域有效提高识别率和计算效率.     

Block-level parallel processing for scaling evenly divisible images

Image scaling is a frequent operation in medical image processing. This paper presents how two-dimensional (2-D) image scaling can be accelerated with a new coarse-grained parallel processing method. The method is based on evenly divisible image sizes which is, in practice, the case with most medical images. In the proposed method, the image is divided into slices and all the slices are scaled in parallel. The complexity of the method is examined with two parallel architectures while considering memory consumption and data throughput. Several scaling functions can be handled with these generic architectures including linear, cubic B-spline, cubic, Lagrange, Gaussian, and sinc interpolations. Parallelism can be adjusted independent of the complexity of the computational units. The most promising architecture is implemented as a simulation model and the hardware resources as well as the performance are evaluated. All the significant resources are shown to be linearly proportional to the parallelization factor. With contemporary programmable logic, real-time scaling is achievable with large resolution 2-D images and a good quality interpolation. The proposed block-level scaling is also shown to increase software scaling performance over four times.     

Parallel Image Processing Technology of Surface Detection System

To improve image processing speed and detection precision of a surface detection system on a strip surface, based on the analysis of the characteristics of image data and image processing in detection system on the strip surface, the design of parallel image processing system and the methods of algorithm implementation have been studied. By using field programmable gate array（FPGA） as hardware platform of implementation and considering the characteristic of detection system on the strip surface, a parallel image processing system implemented by using multi IP kernel is designed. According to different computing tasks and the load balancing capability of parallel processing system, the system could set different calculating numbers of nodes to meet the system＇s demand and save the hardware cost.     

门诊电子病历管理系统的设计与实现

门诊病历是医院病人就医很重要的组成部分,随着医院信息化的不断推进,开发出一款适合医院使用,方便病人就医,能和医院的其他系统很好衔接的门诊电子病历系统已十分必要。在此通过对医院门诊部门进行调研并借鉴大量相关资料,借助Java开发工具设计了可实用的门诊电子病历系统,其中包括系统功能模块的设计与数据库设计,实现了门诊电子病历流程的模块化管理,解决了原有的人工处理系统效率太低与难实现数据共享的问题。     

Linux实时性能优化算法分析与研究

Linux以其内核精悍、功能强大、源代码公开、支持多种硬件平台以及支持丰富的开发工具等特点广泛应用在嵌入式系统领域.作为嵌入式产品的操作系统平台,实时性是一个很重要的目标.基于这个目标提出了一种提高Linux2.6实时性的O（1）算法,该算法设置了新的数据结构及进程调度过程,通过分析Linux 2.6的O（1）算法的时间复杂度,可以得知运用该算法可以极大提高系统的实时性能.     

MPI及其Java实现

随着科学技术的发展，对计算机的并行计算技术的要求越来越高。消息传递接口MPI提供了一种很好的方法。MPI API可以高效地在异构环境中使用，并可以在众多厂商的平台上实现，底层的通信和系统不会有大的改变。java语言是伴随着网络计算技术而诞生的编程语言，它对网络有较好的支持，在网络计算技术中，有着举足轻重的地位。许多分布式应用程序都是由Java开发的。开发一个Java版的MPI很有必要。但MPI论坛未定义MPI的java接口，本文从MPI的基本概念入手，说明了如何用java语言实现MPI。     

Flexible and efficient hardware platform and architectures for waveform design and proof-of-concept in the context of 5G

Several technical contributions are emerging nowadays to fulfill the new requirements foreseen in the 5th generation (5G) of mobile communication systems. Among these contributions, different variants of waveform design are proposed for the new radio air interface as alternative to orthogonal frequency-division multiplexing (OFDM) adopted in 4G. However, in order to prove the feasibility and the benefits of the proposed waveforms, practical hardware implementations are necessary. This paper presents one of the first flexible and efficient hardware platforms for waveform design and proof-of-concept. The proposed platform constitutes a complete hardware/software development environment, with digital processing, radio frequency boards, and all associated interfaces for control, communication, and display. Furthermore, the proposed platform allows the support of several communication scenarios as foreseen in 5G. Promising waveform candidates are implemented, in addition to OFDM, with careful architectural choices to allow fair comparisons. Particularly, this paper presents novel hardware architectures for the UF-OFDM transmitter and receiver.     

A web-based user friendly simulator of optical fiber communication systems

A simulation tool in optical networks design and evaluation is suggested. This user friendly software, baptized “SystemBuild”, is a powerful tool to simulate optical fiber communication systems and can be easily used for both educational and research purposes. People modeling optical networks can use it to investigate the usefulness and the accuracy of their model as well as the performances of the system they intend to implement. This Web-based software needs neither a license nor an installation. Merely, a conventional Internet browser supporting Java plug-in is necessary. Moreover, the software can run in all platforms that include the Java Virtual Machine (jvm). Signals and values can be directly checked by moving the mouse pointer over the component’s connectors allowing an easy debugging and assistance to the users to build a complex system. The quality of collaboration is offered thanks to the free code access to the platform.