一种低电压恒定跨导轨到轨运算放大器的设计

设计了一种低电压恒定跨导的轨到轨运算放大器,作为误差放大器用在BUCK型DC-DC上实现对输出电压的调节。该运算放大器采用两级结构,输入级采用互补差分对的结构,实现了轨到轨电压的输入,并且利用2倍电流镜技术实现了跨导的恒定;输出级采用AB类放大器的结构,提高了输出电压摆幅和效率,实现了轨到轨电压的输出。该电路基于CSMC 0.25μm EN BCDMOS工艺进行设计,仿真结果表明:电源电压为2.8 V时,在输出端负载电容为160 pF、负载电阻为10 kΩ的情况下,增益为124 dB,单位增益带宽积为5.76 MHz,相位裕度为59.9℃,输入跨导为5.2 mΩ~(-1),共模抑制比为123 dB,输入共模信号范围为0～2.8V,输出电压摆幅为0～2.8 V。     

基于单差分对输入级的新型轨到轨运算放大器设计

本文基于CMOS工艺设计了一种新型的轨到轨集成运算放大器。对比分析传统轨到轨输入级设计的优劣,该运放选择采用单差分对输入级结构,使用耗尽型NMOS管作为输入对管,利用耗尽型NMOS管的体效应以及对输入级电路结构的优化,实现轨到轨输入,以AB类输出级结构实现轨到轨输出。经过Cadence仿真验证,工作在5 V单电源供电下,共模输入电压范围可以实现满轨0～5 V,增益高达141.1 dB,带宽1.7 MHz,相位裕度55.4°,具有较低的输入失调电压264μV、输入偏置电流9 pA。整体电路实现了近乎满轨的轨到轨的输出电压摆幅,达到轨到轨运算放大器的设计要求。     

基于单一PMOS差分对的轨到轨输入运算放大器设计

基于国内某CMOS工艺设计了一种单一PMOS差分对的轨到轨输入、恒跨导CMOS运算放大器。输入级电路采用折叠共源共栅结构,通过体效应动态调节输入管的阈值电压扩展共模输入范围到正负电源轨,恒定共模输入范围内的跨导,自级联电流镜有源负载将差分输入转换为单端输出;输出级电路采用AB类结构实现轨到轨输出,线性跨导环确定输出管的静态偏置电流。在5 V电源电压,2.5 V共模电压,1 MΩ负载条件下,经Spectre仿真验证,该运算放大器开环增益为119 dB,相位裕度为58°,共模输入范围为0.0027～4.995 V,共模范围内跨导变化小于3%,实现了轨到轨输入共模范围内的跨导恒定。     

一种恒跨导高增益轨到轨运算放大器

基于TSMC 0.18 μm CMOS工艺,设计了一种新颖的恒跨导高增益轨到轨运算放大器。输入级仅由NMOS管差分对构成,采用电平移位及两路复用选择器控制技术,在轨到轨共模输入范围内实现了输入级恒跨导。中间级采用折叠式共源共栅放大器结构,运算放大器能获得高增益。输出级采用前馈型AB类推挽放大器,实现轨到轨全摆幅输出。利用密勒补偿技术进行频率补偿,运算放大器工作稳定。仿真结果表明,在1.8 V电源电压下,该运算放大器的直流开环增益为129.3 dB,单位增益带宽为7.22 MHz,相位裕度为60.1°,整个轨到轨共模输入范围内跨导的变化率为1.44%。     

恒跨导轨对轨CMOS运算放大器的设计

为了提高运算放大器对电源电压的利用率,基于GSMC 0.18 μm CMOS工艺模型,设计了一种高增益恒跨导轨对轨CMOS运算放大器。该运算放大器的输入级采用了互补差分对,并通过3倍电流镜法保证输入级总跨导在整个共模输入范围内恒定;为了获得较大的增益和输出摆幅,中间级采用了折叠式共源共栅结构;输出级采用了AB类输出控制电路,使输出摆幅基本实现了轨对轨。在3.3 V供电电压以及1.6 V输入电压下,该放大器的直流增益为126 dB,单位增益带宽为50 MHz,相位裕度为65°。电路结构简单,易于调试,可大大缩减设计周期和成本。     

一种高共模抑制比轨到轨全差分运算放大器

针对传统全差分运算放大器电路存在输入输出摆幅小和共模抑制比低的问题,提出了一种高共模抑制比轨到轨全差分运算放大器电路。电路的输入级采用基于电流补偿技术的互补差分输入对,实现较大的输入信号摆幅;中间级采用折叠式共源共栅结构,获得较大的增益和输出摆幅;输出级采用共模反馈环路控制的A类输出结构,同时对共模反馈环路进行密勒补偿,提高电路的共模抑制比和环路稳定性。提出的全差分运算放大器电路基于中芯国际(SMIC) 0.13μm CMOS工艺设计,结果表明,该电路在3.3 V供电电压下,负载电容为5 pF时,可实现轨到轨的输入输出信号摆幅;当输入共模电平为1.65 V时,直流增益为108.9 dB,相位裕度为77.5°,单位增益带宽为12.71 MHz;共模反馈环路增益为97.7 dB,相位裕度为71.3°;共模抑制比为237.7 dB,电源抑制比为209.6 dB,等效输入参考噪声为37.9 nV/Hz^1/2@100 kHz。     

全摆幅运算放大器的设计

设计了一种全摆幅输入的运算放大器。通过恒定跨导结构实现互补输入差分对共模输入电压在轨到轨范围内对恒定跨导的控制。设计中在输出结构里使用了电流求和电路,以达到输出信号相加,实现单端输出的功能。采用Spectre进行仿真,电源电压5V时,低频增益84dB,单位增益带宽12MHz。     

一种恒跨导轨对轨CMOS运算放大器的设计

设计了一种新颖的恒跨导轨对轨CMOS运算放大器结构。输入级采用轨对轨的结构,在输入级采用4个虚拟差分对管来对输入差分对的电流进行限制,使运放的输入级跨导在工作范围内保持恒定。输出级采用前馈式AB类输出结构,以使输出达到全摆幅。仿真结果显示,在5 V电源电压和带有10 pF电容与10 kΩ电阻并联的负载下,该运放在共模输入范围内实现了恒跨导,在整个共模输入范围内跨导变化率仅为3%,输出摆幅也达到了轨对轨全摆幅,运放的开环增益为108.5 dB,增益带宽积为26.7 MHz,相位裕度为76.3°。     

低功耗轨至轨CMOS运算放大器设计

设计了一个1.5 V低功耗轨至轨CMOS运算放大器。电路设计中为了使输入共模电压范围达到轨至轨性能,采用了NMOS管和PMOS管并联的互补差动对输入结构,并采用成比例的电流镜技术实现了输入级跨导的恒定。在中间增益级设计中,采用了适合在低压工作的低压宽摆幅共源共栅结构;在输出级设计时,为了提高效率,采用了简单的推挽共源级放大器作为输出级,使得输出电压摆幅基本上达到了轨至轨。当接100 pF电容负载和1 kΩ电阻负载时,运放的静态功耗只有290μW,直流开环增益约为76 dB,相位裕度约为69°,单位增益带宽约为1 MHz。     

一种低失调CMOS轨到轨运算放大器研究

基于CMOS工艺设计了一款轨到轨运算放大器,整体电路包括偏置电路、输入级、输出级以及ESD保护电路。电路中的输入级使用了一种全新的架构,通过一对耗尽型NMOS管作为输入管,实现轨到轨输入,同时在输入级采用了共源共栅结构,能够提供较高的共模输入范围和增益;在输出级,为了得到满摆幅输出而采用了AB类输出级;同时ESD保护电路采用传统的GGMOS电路,耐压大于2 kV。经过仿真后可知,电路的输入偏置电流为150 fA,在负载为100 kΩ的情况下,输出最高和最低电压可达距电源轨和地轨的20 mV范围内,当电源电压为5 V时能获得80 dB的CMRR和120 dB的增益,相位裕度约为50°,单位增益带宽约为1.5 MHz。     

An enhanced folded cascode Op-Amp using positive feedback and bulk amplification in 0.35 μm CMOS process

In this paper a new operational amplifier is presented which is based on the conventional folded cascode Op-Amp structure. A new method of positive feedback is used to increase dc-gain. This method does not limit the range of the output voltage swing. True performance of the Op-Amp in higher output voltage swings is another advantage of the proposed Op-Amp in comparison with the conventional structures. Bulk amplification and positive feedback are used to improve the Op-Amp specifications. Proposed structure has been simulated by HSPICE software using level 49 parameters (BSIM3v3) in a typical 0.35 μm CMOS technology. The HSPICE simulation confirms the theoretical estimated improvements.     

改进型折叠式共源共栅运算放大器电路的设计

在套筒式共源共栅、折叠式共源共栅运放中,折叠式共源共栅运算放大器凭借较大的输出摆幅和偏置电压的较低等优点而得到广泛运用。但是,折叠式的这些优势是以牺牲较大的功耗、较低的电流利用率而换取的。本文以提高电流利用率为着手点设计了一种改进的折叠式共源共栅运算放大器,在相同的电压和负载下改进的折叠式共源共栅运算放大器能显著提升跨导、压摆率和噪声性能。仿真结果表明在相同功耗和面积的条件下,改进的折叠式共源共栅运算放大器的单位增益带宽和压摆率是折叠式共源共栅运放的3倍。     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

基于迟滞比较器的过热保护电路设计

为了防止芯片过热,提高芯片可靠性和稳定性,采用0.5μm CMOS工艺,设计了一种具有迟滞比较器的过热保护电路。由于采用了折叠式运放,使得比较器输入范围更大,灵敏度和迟滞性能更好。利用Cadence Spectre仿真工具对电路进行了仿真,结果表明电源电压为4.5～7 V时,过温保护阈值变化量极小,表现出输出信号对电源的良好抑制。当温度超过130℃时,输出信号翻转,芯片停止工作;温度降低至90℃时,芯片恢复工作。此电路可以通过调整特定管子的尺寸而控制两个阈值电压的大小,从而避免热振荡的发生。     

Sub-1-V Supply Self-Adaptive CMOS Image Sensor Cell With 86-dB Dynamic Range

This letter presents a high dynamic range CMOS active pixel structure operating at a sub-1-V supply voltage, which is implemented using a standard 0.18-mum CMOS logic process. In order to improve the output voltage swing range and associated pixel dynamic range at a low supply voltage, a pMOS reset structure is incorporated into the pixel structure along with a photogate pixel structure based on the self-adaptive photosensing operation. At a low supply voltage of 0.9 V, the new pixel provides an output voltage swing range of 0.41 V and a high dynamic range of 86 dB, which is the highest among the reported pixel structures up to date operating at sub-1-V     

A very low output resistance and wide-swing class-AB level-shifted folded flipped voltage follower cell

The paper presents a class-AB flipped voltage follower (FVF) cell. In contrast to previous works in the literature, FVF cell, level shifter and folded FVF cell are merged in the proposed FVF cell to offer class-AB operation along with wide input/output voltage swing and low output resistance. In the proposed FVF cell, the level shifter increases the input/output voltage swing while the folding transistor provides an alternate path for sourcing current, which results in low output resistance. The proposed FVF cell offers wide input/output voltage swing of 0.80 V/0.67 V, high gain of 0.84, wide bandwidth of 54 MHz for the worst case load capacitance of 50 pF and low output resistance of 10 Ω. The proposed FVF cell is simulated using Cadence Virtuoso Analog Design Environment in 180 nm CMOS technology. The physical layout has been designed using Cadence Virtuoso Layout XL editor and post-layout simulation results are presented to demonstrate the performance of the proposed FVF cell. The corner analysis has also been performed to show the robustness of the proposed FVF cell.     

一种0.8V衬底驱动轨对轨运算放大器设计

采用衬底驱动技术设计低压低功耗轨对轨运算放大器。输入级采用衬底驱动MOSFET,有效避开阈值电压限制,将电源电压降至0.8V,实现低压下轨对轨共模输入范围。增加衬底驱动冗余差分对及反折式共源共栅求和电路实现恒定跨导控制,消除共模电压对输入级跨导的影响,输出采用前馈式AB类输出级,以提高动态输出电压范围。基于标准0.18μmCMOS工艺仿真运放,测得输出范围0.4～782.5mV,功耗48.8μW,电源抑制比58dB,CMRR65dB,直流开环增益63.8dB,单位增益带宽2.4MHz,相位裕度68°。版图设计采用双阱交叉空铅技术,面积为97.8μm×127.6μm。     

A class-B output buffer for flat-panel-display column driver

Due to the large number of output buffers on a column driver chip of a flat-panel display, the quiescent current and die area of the output buffer must be minimized. This paper presents a low static power, large output swing, and wide operating voltage range class-B output buffer amplifier for driving the large column line capacitance in a flat-panel display. A comparator is used in the negative feedback path to eliminate quiescent current in the output stage. The proposed output buffer circuit was implemented in a 0.8 μm CMOS process. Its output voltage swing is from 1 V to the supply voltage. With 5 V supply and 600 pF load, the maximum tracking error is ±7 mV. The measured static current is 24 μA. The settling time for 4 V swing to within 0.2% is 8 μs, which is more than adequate for driving 1280×1024 pixels liquid crystal displays with 86 Hz frame rate and 256 gray levels in each color     

A wide-band high-voltage monolithic amplifier

A monolithic amplifier capable of 80-V swing and 1.7-V/NS slew rate has been fabricated using standard integrated circuit techniques. The amplifier is intended for capacitive loads such as in electrostatic deflection applications. The totem-pole technique is combined with active feedback to produce this large voltage swing without excessive power consumption. A new output circuit linked with a floating current source is used to supply large accurate positive and negative charging currents over a large dynamic range. The amplifier voltage range is extendable by increasing the degree of stacking in the totem-pole arrangement.     

一个自偏压互补折叠式共源共栅放大器的设计

对传统CMOS折叠式共源共栅运算放大器进行分析和总结,利用自偏压互补折叠技术实现了一种高性能CMOS自偏压互补折叠式共源共栅运算放大器。这个设计消除了6个外部偏置电压,减小了供电电压,并且提高了输出摆幅和开环增益,同时,使用这个方案还可以使芯片面积、功耗、偏置部分对噪声和串扰的灵敏度降低,最后描述了设计过程并给出了设计的仿真结果,证实该结构的可行性。