MOSFET thermal noise modeling for analog integrated circuits

The effects of device geometry, oxide thickness, and bias condition on the thermal noise of MOSFET's are investigated. The experimental results show that the conventional MOSFET thermal noise models do not accurately predict the thermal noise of MOSFET's. A model that is capable of predicting the thermal noise of both long and short channel devices in both the triode and saturation regions is presented. This model, which can be easily implemented into existing circuit simulators such as SPICE, has been verified by a wide variety of measurements     

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

The integration of chips in the third dimension has been explored to address various physical and system level limitations currently undermining chip performance. In this paper, we present a comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane. We also analyze the impact of technology scaling on TSV electrical parasitics, and investigate the power and delay trend in 3-D interstratum IO drivers with those of global wire in 2-D circuits over various technology nodes. We estimate the global wire length necessary to produce an equivalent 3-D IO delay, a metric useful in early stage design tools for 3D floorplanning that considers the electrical characteristics of 3D connections with TSVs and microconnects.     

Thermal characteristic of Cu-Cu bonding layer in 3-D integrated circuits stack

Copper (Cu) thermo-compression bonding of wafers can be used to fabricate multi-layer three-dimensional (3-D) integrated circuits (ICs). This work examines the thermal characteristic of the Cu bonding layer and demonstrates experimentally that Cu bonding layer can act as a spreading layer that helps in heat dissipation of bonded 3-D ICs stack more efficiently compared to silicon dioxide bonding layer. The use of Cu bonding layer in a double-layer stack of ICs provides better cooling by as much as 9 °C compared to oxide bonding interface.     

Well-posed nonlinear problems in integrated circuits modeling

In this paper we study the problem (E) + (BC) + (IC) (see below) which represents a model for integrated circuits. We assume that the distributed parametersr(x) andc(x) are nonconstant, dielectric leakages depend on thex-coordinate as well as the voltage level, while the interconnecting multiport is nonlinear and possibly multivalued.     

FD-TD modeling of digital signal propagation in 3-D circuits withpassive and active loads

Most existing computer-aided circuit design tools are limited when digital clock speeds exceed several hundred MHz. These tools may not deal effectively with the physics of UHF and microwave electromagnetic wave energy transport along metal surfaces such as ground planes or in the air away from metal paths that are common at or above this frequency range. In this paper, we discuss full-wave modeling of electronic circuits in three dimensions using the finite-difference time-domain (FD-TD) solution of Maxwell's equations. Parameters such as stripline complex line impedance, propagation constant, capacitance per unit length and inductance per unit length can be easily computed as a function of frequency. We also discuss FD-TD Maxwell's equations computational modeling of lumped-circuit loads and sources in 3-D, including resistors and resistive voltage sources, capacitors, inductors, diodes, and transistors. We believe that this approach will be useful in simulating the large-signal behavior of very high-speed nonlinear analog and digital devices in the context of the full-wave time-dependent electromagnetic field     

Crosstalk reduction in mixed-signal 3-D integrated circuits with interdevice layer ground planes

We show nearly 8 dB of crosstalk reduction using ground planes between active device layers in three-dimensional (3-D) integrated circuits. Our experimental work utilizes two planes of MOS transistors with tungsten or polysilicon ground planes designed to attenuate crosstalk. Theoretical simulations, using an electromagnetic solver, and the experimental results are consistent with analytical results. The key result verified is that a ground plane, whose footprint shadows the device area, is sufficiently large for effective attenuation. The interdevice layer ground plane provides an effective means to achieve crosstalk reduction in 3-D mixed-signal/RF integration because of simple fabrication and high coupling isolation.     

Thermally-aware modeling and performance evaluation for single-walled carbon nanotube-based interconnects for future high performance integrated circuits

Given the performance and reliability limits of conventional copper interconnects in the tens of nanometer regime, carbon-nanotube (CNT) based interconnects emerge as a potential reliable alternative for future high performance VLSI industry. In this paper, we present an accurate thermally-aware model for single-walled carbon-nanotube (SWCNT) based interconnects. Our thermally-aware model is an integration of temperature-dependent electrical parasitics model and thermal equivalent circuit that captures both self-heating and heat conduction phenomena. We verify the accuracy of our electro-thermal model against recently reported experimental measurements. By leveraging the presented electro-thermal model, we present a simulation platform to estimate the performance of SWCNT-based interconnects under different temperature conditions. Our thermally-aware model achieves improvement in the delay estimation accuracy of about 51.3% on average. Based on our simulation results, SWCNT-based interconnects offer more than 5×reduction in delay at dimensions of about 10-20 nm for 27- 127 °C temperature range.     

Stochastic interconnect modeling, power trends, and performancecharacterization of 3-D circuits

Three-dimensional (3-D) technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. One of the purposes of realizing 3-D integration is to reduce the interconnect complexity and delay of two dimensions (2-D), which are widely considered as the barriers to continued performance gains in future technology generations. Thus, understanding the interconnect and its related issues, such as the impact on circuit performance, is key to 3-D circuit applications. In this paper, we present a stochastic 3-D interconnect model and study the impact of 3-D integration on circuit performance and power consumption. To model 3-D interconnect, we divide 3-D wires into two parts (horizontal wires and vertical wires) and derive their stochastic distributions. Based on those distributions, we estimate the delay distribution. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the number of repeaters, and dramatically improve circuit performance. With 3-D integration, circuits can be clocked at frequencies much higher (double or even triple) than 2-D     

MOS Integrated circuits fabricated on multilayer heteroepitaxial silicon-insulator structures for applications to 3-D integrated circuits

Multiple layers of single-crystal silicon and boron phosphide have been grown on silicon and silicon-on-sapphire substrates. Up to four layers have been grown on silicon and two layers on silicon-on-sapphire. The quality of the silicon layers was confirmed by fabricating PMOS integrated circuits on the top silicon layer in all of these structures. The integrated circuits contained individual transistors, p-n diodes, inverters, flip-flops, and ring oscillators. All circuits successfully operated on all of the layers tested. The transistor mobilities tended to drop as more layers were added to the structure. The delay time of the ring oscillators rose as the number of layers increased reflecting the drop in transistor mobilities. By fabricating circuits on the various layers, the quality of the individual layers has been shown to be sufficiently high to consider this material combination as a possible candidate for 3-D integrated circuits. The boron phosphide was used not only as an insulator but also for the fabrication of vertical resistors and p-n junctions.     

Noise associated with distributed resistance of MOSFET gate structures in integrated circuits

The effect of thermal voltage fluctuations in a resistive gate matrix perpendicular to the direction of channel current, in a MOSFET, are treated in detail. A general formula is derived to arrive at channel current fluctuations for an arbitrary gate matrix layout. This formulation is an extension of the analysis done by Thornber and is valid for frequencies at which the distributed RC time constants associated with the gate matrix are not important. The results of this analysis can be used to design low-noise resistive gate structures.     

器件参数宏模型的精确建立及其在模拟集成电路性能建模与优化中的应用

Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presented to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven （OPD） metamodels of MOSFETs are introduced to capture the circuit＇s characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs. The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.     

Accurate metamodels of device parameters and their applications in performance modeling and optimization of analog integrated circuits

Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presnted to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven (OPD) metamodels of MOSFETs are introduced to capture the circuit's characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs.The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.     

Efficient modeling of 3-D photonic crystals for integrated optical devices

We propose a full-wave numerical model of a three-dimensional (3-D) photonic crystal with the absolute photonic bandgap (PBG) centered at /spl lambda//spl sim/1.6 /spl mu/m. The analyzed structure is widely used in integrated optical circuitry. The electromagnetic analysis is performed by using the finite-element method (FEM) and transmission line matrix-integral equation (TLMIE) method. We analyze the reflection properties and compare theoretical results to experimental data. Due to its exact boundary conditions, TLMIE shows much higher accuracy with respect to FEM in the PBG optical band. As a demonstration, we have realized and analyzed a holographic polymer dispersed liquid crystal grating.     

The modeling of resistive interconnects for integrated circuits

Techniques for analyzing the signal transmission properties of long resistive interconnects on integrated circuits are presented. Because accurate measurements of propagation characteristics on chip are difficult to make, RC transmission line theory is used to establish exact performance. The results of various simulations are compared to this theoretical performance. Guidance is provided for selecting the number of elements needed to accurately simulate performance under various conditions.     

Technology and performance of integrated complementary MOS circuits

The desirable characteristics of complementary MOS circuits are low standby power consumption, high speed, and high noise immunity. These require close control and matching of n- and p-channel transistor characteristics. Acceptable limits for mismatch between devices were derived based on circuit considerations and were related to process variables. Predicted performances were achieved using test circuits; feasibility of the technology has been shown. The reliability of fabricated test structures was evaluated.     

Harmonic performance of single-channel MOS integrated circuits

Using simple square-law models for both the MOSFET current-voltage characteristics and the relationship between the threshold voltage and the source-to-substrate voltage, simple expressions are presented for predicting the performance of the basic MOSFET circuits used in analog MOS technology. Using these expressions, the low-frequency gain and the second and third harmonic distortion performance of the enhancement-load inverters, enhancement-load source follower, depletion-load inverter, and depletion-load source follower can be easily predicted by hand calculations. The results obtained by using these expressions are compared with previously published measurements and calculations.     

A simple approach to modeling cross-talk in integrated circuits

A simple engineering approach for rapid simulation of cross-talk in mixed-mode IC's using SPICE is presented. A side-by-side comparison of several cross-talk reduction schemes has shown that while an SOI-based process provides high isolation from cross-talk at low operating frequencies, its benefit is lost at high frequencies. Simple guard ring substrate contacts appear to be the technique best suited for preventing cross-talk at high operating frequencies. Lumped parameter equivalent circuits have also been developed to represent different isolation schemes in SPICE. The isolation characteristics of test structures employing the above techniques are computed using SPICE and the results compared with two-dimensional device simulation. The results are also compared with experimental measurements on actual silicon to validate the models     

Analysis of integrated circuits thermal dynamics with point heating time

The article presents an analysis of thermal dynamics in integrated circuits using a new method. The introduced variable that defines the dynamic state of an IC is point heating time (PHT). The authors examine the dynamic behaviour of the integrated circuit caused by the thermal activity of one and many functional modules on the multi-core chip. Various substrate materials were analysed and the PHT value was compared to the mean temperature of the integrated circuit and its time constant. The PHT value is also analysed as a variable dependent on the distance from the heat centre of the heating module. The analytical equation, which is a result of the analysis, can describe the PHT value versus distance for the whole chip surface. Further analysis helps verify the hypothesis using a massive multi-core integrated circuit. The result can be used to increase the thermal efficiency of multi-core integrated circuits by thermal-aware flow modification of the scheduling algorithm.     

Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space

Three-dimensional (3-D) integrated circuits (ICs), with multiple stacked device layers, offer a unique design opportunity to use both bulk and partially depleted (PD) silicon-on-insulator (SOI) CMOS devices in a single circuit design. Such 3-D designs can, for example, minimize the body effect common in bulk designs and reduce adverse floating-body effects (FBE) common in PD SOI designs. Sequential 3-D technology such as exfoliation-based single-crystal silicon layer transfer allows a low-temperature approach to 3-D integration with high-density interconnectivity. Using the characteristics of this technology, we present the mixed SOI bulk (MSB) design approach that effectively re-maps conventional VLSI designs to the 3-D design space. Tradeoffs in delay, noise margin, power, and circuit footprint are analyzed and demonstrated through analyzes of static, dynamic, pass-transistor, and SRAM circuits.