基于SvstemC的支持异源通信实体的NoC仿真架构

片上网络为具有多个处理单元的高速并行片上系统提供一种结构化的片上通信与互连的方法。当前丰富多样的通信实体的选择、建模和仿真，对于精确评估和优化片上网络的整体性能非常重要。本文提出了一种基于SystemC的片上网络仿真和评估构架，以结构化、自动化的方式，支持基于当前通信实体的NoC仿真和设计流程。     

基于SystemC的UART设计

随着集成电路设计规模的不断扩大,SOC设计的时代已经到来。SystemC作为一种新兴的SOC设计语言,它本质上是在C++的基础上添加的硬件扩展库和仿真核,这使得SystemC可以建模不同抽象级别的包括软件和硬件的复杂电子系统。在C++环境中,它支持软件、硬件和接口描述。利用SystemC的这些特性实现了对UART的建模,并用波形图验证了仿真结果。     

MPSoC上的NoC通信架构的实现

本文介绍了片上网络的相关概念,采用2D Mesh拓扑结构和XY路由算法,实现了一款用于构建MPSoC的片上网络.通过在EDK中构建4个MicroBlaze核的处理器,并用片上网络进行连接,最终在XUP Virtex-ⅡPro FPGA开发板上验证了片上网络的正确性.     

基于SystemC的片上网络仿真实验研究

本文分析了基于SystemC的片上网络软件仿真平台。我们以NIRGAM模拟器为例,实现并评估了JPEG编码器和XYYX路由算法,体现了NIRGAM软件模拟器方便的扩展能力及性能评估能力。实例表明,片上网络采用软件模拟提供了更灵活的实验方式,缩短了设计和验证的周期,有利于培养创新能力。     

基于BIST的NoC系统通信链路测试研究

采用内建自测试技术,完成了对NoC系统通信链路的测试。测试内容包括路由节点与其之间链路的测试,以及其与资源节点之间链路的测试。文中用硬件描述语言Verilog HDL完成各个测试模块的设计,用Quartus II软件自带的逻辑分析仪在基于FPGA的NoC系统硬件平台上完成测试。该测试方法不仅提高了故障覆盖率,还大幅降低了测试时间。     

片上网络的SystemC建模研究

为了实现软硬件协同设计和提高仿真速度的需求,采用SystemC语言的建模方法,通过对片上网络体系结构的研究,提出了一种片上网络的建模方案,并对一个mesh结构完成了SystemC的建模设计。该模型可在系统级和寄存器传输级上使用同一个测试平台,且具有仿真速度快的特点,达到了设计要求。     

一种基于SystemC的片上网络建模与仿真方法

随着芯片上集成度的提高,设计复杂性和时钟同步的问题也越来越严重,因此,面向通讯为中心的片上网络(NoC)将成为未来片上互连的主要方式.由此建立了一种可对路由内部单元细化配置的片上网络模拟器:采用分组数据的虫孔(Wormhole)交换策略,使用仿真速度较快的SystemC事务级语言搭建了片上网络模型.同时提出了一种较为精确的仿真方法,模拟结果显示能适用于多核结构的片上网络的模拟仿真.     

基于NoC的众核处理器可靠性仿真分析研究

随着半导体制造工艺的发展,众核芯片上的晶体管密度不断增加,随之而来的寿命可靠性问题日益严重。为了准确评估芯片的可靠性,本文提出了一种基于蒙特卡洛方法的系统级可靠性仿真框架,并在此基础上研究了No C通信架构对可靠性的影响。实验结果表明,如果不考虑众核芯片的No C通信结构,系统级可靠性评估的相对偏差最高可达到60%左右。     

基于NoC架构的软件无线电验证平台设计

软件无线电技术可以满足新一代无线通信系统对可扩展性、可重配置性以及可升级性的要求,并且能够解决各种通信体制之间的兼容性等问题,因而被认为是未来移动通信的关键技术之一。本文设计了一个基于NoC架构的软件无线电验证平台。该平台的硬件部分是一个16节点的4×42-D mesh NoC多核结构,NoC底层采用虫洞交换、确定路由、输出缓存队列（Virtual Output Queue,VOQ）机制,以及全新设计的网络接口（Network Interface,NI）完成硬件底层和处理器核之间的数据交互。通过改变运行在处理器核上的软件代码可以实现各种无线电收发系统的功能。根据正交频分复用（OFDM）基带收发系统在该验证平台上的验证与实现,证明本设计是一个高效、可靠、灵活的软件无线电验证平台。     

面向通信能耗的3D NoC映射研究

对于传统的平面结构,三维片上网络(3D NoC)具有更好的集成度和性能,在单芯片内部可以集成更多的处理器核。3D NoC作为2D NoC的结构拓展,在性能提高和低功耗设计方面更具优越性,成为多核系统芯片结构的主流架构。映射就是应用某种算法寻找一种最优方案,将通信任务图的子任务分配到NoC的资源节点上,保证NoC的通信能耗最小。参照2D NoC的研究方法,提出了针对3D网格NoC的通信能耗模型,采用蚁群算法实现了面向通信能耗的NoC映射。实验结果表明,面向不同网络规模的3D网格NoC平台,蚁群映射同随机映射相比,通信能耗降低可以达23%～42%。     

A Simulation Framework for Evaluating Interference Mitigation Techniques in Heterogeneous Cellular Environments

Femtocells present an attractive solution for the improvement of a mobile network’s services providing better data rates and coverage. Since their deployment results to a heterogeneous network where two layers must utilize the available spectrum, issues of interference arise. A method to address this challenge, is investigating the locations of the newly installed FBS, and enforcing a power controlled transmission of all FBSs that achieves optimal and fair overall performance. Another option that becomes available in inter-cell interference cancellation (ICIC) macrocell environments, is utilizing the available spectrum to complete or partly avoid co-channel operation. In this work, we provide a simulation framework that allows the creation of custom, high configurable, user defined topologies of femtocells with power control and frequency allocation capabilities. It allows the investigation of the margin of improvement in interference when these methods are applied and may work as a decision tool for planning and evaluating heterogeneous networks. To showcase the framework’s capabilities, we evaluate and study the behaviour of custom deployed femtocells/macrocells networks and examine the cross-tier interference issues. Facilitated by the framework, we enforce and evaluate each interference mitigation technique for different femtocells’ deployment densities. Finally, we compare the results of each method in terms of total throughput, spectral efficiency and cell-edge users’ performance.     

A Security Framework for NoC Using Authenticated Encryption and Session Keys

Network on Chip (NoC) is an emerging solution to the existing scalability problems with System on Chip (SoC). However, it is exposed to security threats like extraction of secret information from IP cores. In this paper we present an Authenticated Encryption (AE)-based security framework for NoC based systems. The security framework resides in Network Interface (NI) of every IP core allowing secure communication among such IP cores. The secure cores can communicate using permanent keys whereas temporary session keys are used for communication between secure and non-secure cores. A traffic limiting counter is used to prevent bandwidth denial and access rights table avoids unauthorized memory accesses. We simulated and implemented our framework using Verilog/VHDL modules on top of NoCem emulator. The results showed tolerable area overhead and did not affect the network performance apart from some initial latency.     

针对片上网络组播通信模型的设计与仿真

文章提出了一种针对片上网络的组播通信模型,能够为片上网络提供无死锁的通信.该模型能显著减少总通信量,增加通道利用率;在测试模式下,能有效节省测试时间.将该模型仿真应用到二维带环网格拓扑结构的片上网络中,试验结果表明,该模型较单播通信具有更小的平均传输延迟和更高的吞吐量.     

一种支持多协议的开放互操作框架

在不改变支撑环境基础结构的前提下,根据不同应用需求定制或扩展不同互操作协议,是中间件异构问题的解决方案之一.本文提出了一种支持多协议的开放互操作框架,其核心在于将构件化的思想引入框架的设计以及协议的实现中,将协议的主要功能封装为构件,通过框架增加、删除、替换相关构件,就能实现互操作协议的定制与扩展.论文实现了互操作框架以及主流互操作协议,并给出性能评测.     

An Adaptive Heterogeneous Runtime Framework for Irregular Applications

Future computing devices are likely to be based on heterogeneous architectures, which comprise of multi-core CPUs accompanied with GPU or special purpose accelerators. A challenging issue for such devices is how to effectively manage the resources to achieve high efficiency and low energy consumption. With multiple new programming models and advanced framework support for heterogeneous computing, we have seen many regular applications benefit greatly from heterogeneous systems. However, migrating the success of heterogeneous computing to irregulars remains a challenge. An irregular program's attribute may vary during execution and are often unpredictable, making it difficult to allocate heterogeneous resources to achieve the highest efficiency. Moreover, the irregularity in applications may cause control flow divergence, load imbalance and low efficiency in parallel execution. To resolve these issues, we studied and proposed phase guided dynamic work partitioning, a light-weight and fast analysis technique, to collect information during program phases at runtime in order to guide work partitioning in subsequent phases for more efficient work dispatching on heterogeneous systems. We implemented an adaptive Runtime System based on the aforementioned technique and take Ray-Tracing to explore the performance potential of dynamic work distribution techniques in our framework. The experiments have shown that the performance gain of this approach can be as high as 5 times faster than the original system. The proposed techniques can be applied to other irregular applications with similar properties.     

基于SOA架构的异构数据库整合框架

以SOA为基础,ESB为消息传递总线,通过两级建模,将不同数据库系统、不同操作系统、不同语义结构的数据资源进行整合,使得用户通过统一管理平台能够对多个数据库资源进行访问,让用户如同访问一个数据库系统一样.从而提高信息资源整体使用效率,有利于实现信息资源的共享.     

A Multilayer Framework Supporting Autonomous Run-Time Partial Reconfiguration

A multilayer run-time reconfiguration architecture (MRRA) is developed for autonomous run-time partial reconfiguration of field-programmable gate-array (FPGA) devices. MRRA operations are partitioned into logic, translation, and reconfiguration layers along with a standardized set of application programming interfaces (APIs). At each level, resource details are encapsulated and managed for efficiency and portability during operation. In particular, FPGA configurations can be manipulated at runtime using on-chip resources. A corresponding logic control flow is developed for a prototype MRRA system on a Xilinx Virtex II Pro platform. The Virtex II Pro on-chip PowerPC core and block RAM are employed to manage control operations while multiple physical interfaces establish and supplement autonomous reconfiguration capabilities. Evaluations of these prototypes on a number of benchmark and hashing algorithm case studies indicate the enhanced resource utilization and run time performance of the developed approaches.