Technology and design challenges of MOS VLSI

The past decade of MOS technology has been characterized by the scaling of Si-gate LOCOS NMOS to ever smaller geometries. However, NMOS circuits with 1 /spl mu/m geometries will not be achieved by continued direct scaling of this structure. Major changes will be required in the 1-2 /spl mu/m range in terms of: 1) process and structure enhancements that will be required to realize the performance advantages predicted by scaling, and 2) new physical phenomena that will become important in determining MOSFET behavior. The 1-2 /spl mu/m range of NMOS technology is referred to as the `1.25 /spl mu/m discontinuity'. Both aspects of this discontinuity are explored, and some projections for MOS are made for the next decade.     

MOS transistor modeling for RF IC design

This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. The subcircuit includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance Y22. The bias and geometry dependence of the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the Y parameters are established and compared to measurements made on a 0.25-μm CMOS process. The Y parameters and transit frequency simulated with this scalable model versus frequency, geometry, and bias are in good agreement with measured data. The nonquasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices used for the S-parameter measurement     

On the short-channel theory for MOS transistor

An attempt is made to derive rigorous analysis for the short-channel MOS transistor on the basis of the 2-D Poisson's equation. The analysis is able to predict a correct dependence of the threshold voltage on channel length and drain voltage, avoids the need for the definition of an average depletion charge density, and gives more physical insight into the short-channel effects     

An MOS transistor model for analog circuit design

This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model     

Photoresponses of MOS transistor

Illumination effects on the drain current were studied for a p-channel enhancement-type MOS transistor, and the results show that the photoresponses are mainly due to electron excitation in the conduction band from surface states lying near the top of the valence band. It also appears that the hole density of the channel decresses in the vicinity of the drain region but is almost constant over the entire channel when more than 200 µm away from the drain edge.     

On the small-signal behaviour of the MOS transistor in quasistatic operation

A complete MOST small signal model is proposed, chosen to related most easily to widely used incomplete models. For quasistatic operation, expressions for the model parameters valid for all regions of operation, including weak and moderate inversion, are derived. The predicted bias dependence of the nine model capacitance coefficients, derived starting from the long channel MOST theory recently presented by F. Van de Wiele, is presented and compared to available experimental data.     

Selective low-pressure silicon epitaxy for MOS and bipolar transistor application

The selective low-pressure epitaxy is presented in this paper. In contrast to LOCOS technology, this process starts with structuring a thick field oxide by anisotropic RIE etching. Then monocrystalline silicon is grown selectively in the windows formed. Si-gate MOS transistors have been produced using this technology. In the field of bipolar transistors, reactive ion etching and selective low-pressure epitaxy has been used to optimize the Schottky collector transistor to a nearly one-dimensional structure. These transistors have been built on a submicrometer epitaxial layer.     

An accurate large-signal MOS transistor model for use in computer-aided design

Some MOS transistor models for computer-aided design, each having a given accuracy and complexity, are presented. These models apply before saturation and in the saturation region. Before saturation, the proposed theory takes into account the behavior of mobility versus gate-channel and drain-source biases. In the saturation region the effect of mobile carriers on the drain-channel space-charge layer in an approximate two-dimensional analysis is taken into account. This model has been checked for dc characteristicsI_{D} (V_{DS})and different channel lengths, dynamic resistances in the saturation region, transfer characteristics of various inverters, and dynamic response of these circuits. The accuracy is within 5 percent.     

钟控神经MOS管的改进及其在多值电路中的应用

首先对钟控神经MOS管进行研究,提出了相应的改进方法.然后采用此改进的钟控神经MOS管设计了一种新型多值触发器.与传统的触发器相比较,此多值触发器具有结构简单、速度快、功耗低等特点;而且无需改变电路结构就可实现不同基的多值触发器.PSPICE模拟证明了所设计的电路具有正确的逻辑功能.     

Evolution of the MOS transistor-from conception to VLSI

Historical developments of the metal-oxide-semiconductor field-effect transistor (MOSFET) during the last 60 years are reviewed, from the 1928 patent disclosures of the field-effect conductivity modulation concept and the semiconductor triode structures proposed by Lilienfeld to the 1947 Shockley-originated efforts which led to the laboratory demonstration of the modern silicon. MOSFET in 1960. A survey is then made of the milestones of the past 30 years leading to the latest submicron silicon logic CMOS (complementary MOS) and BICMOS (bipolar-junction transistor CMOS combined) arrays and the three-dimensional and ferroelectric extensions of Dennard's one-transistor dynamic random access memory (DRAM) cell. The status of the submicron lithographic technologies is summarized. Future trends of memory cell density and logic gate speed are projected. Comparisons of the switching speed of the silicon MOSFET with that of silicon bipolar and GaAs field-effect transistors are reviewed. The use of high-temperature superconducting wires and GaAs-on-Si monolithic semiconductor optical clocks to break the interconnect-wiring delay barrier is discussed     

Extraction of series-resistance-independent MOS transistor modelparameters

It is shown by simulations and experiments how series-resistance-independent intrinsic SPICE level-3 MOS parameters can be extracted when the source and drain series resistance is extracted as a separate parameter. If this resistance is not extracted separately, not only will the mobility reduction factor depend on the series resistance but so will the maximum drift velocity, the saturation field factor, and the static feedback factor. External source and drain resistors have been used to investigate how these parameters depend on the series resistance     

神经元晶体管的研究进展

神经元晶体管是20世纪90年代初发展起来的一种新型功能器件，具有在栅上对所有输入信号进行加权求和的功能，有广泛的电路应用范围。文章介绍了神经元晶体管的产生背景、基本结构和工作原理；并对其发展现状和未来趋势进行了深入的讨论。     

Direct extraction of MOS transistor model parameters

The direct extraction method of MOS transistor parameters is summarized and results from its application to the first Norchip 1µm CMOS process run are presented. Two different transistor models (SPICE level 3 and BSIM) have been used, and both models are found to be useful at least down to 1µm devices: typical average relative errors between measured and calculated currents are in the 2-9% range. Two methods of calculating the difference between drawn and effective geometries have been compared. The influence of the source/drain series resistance is also discussed.     

An easy-to-use mismatch model for the MOS transistor

In this paper, a physics-based mismatch model is presented. It is demonstrated on a 0.18-/spl mu/m technology that a simple mismatch model can still be used to characterize deep-submicron technologies. The accuracy of the model is examined and found to be within 20% in the strong inversion region. Bulk bias dependence is modeled in a physical way. To extract the mismatch parameters, a weighted fit is introduced. It is shown that the width and length dependence of the mismatch parameters is given by the Pelgrom model.     

Implementation of fully self-aligned bottom-gate MOS transistor

This letter reports the implementation of a bottom-gate MOSFET, which possesses the following fully self-aligned structural features: 1) self-aligned source-drain to bottom-gate; 2) self-aligned thick source-drain and thin channel; and 3) self-aligned and mask-free lightly doped drain (LDD). The complete self-alignment is realized by combining a conventional ion implantation and a subsequent chemical-mechanical polishing (CMP) step. The process is applied to poly-Si films crystallized from an a-Si film deposited by LPCVD using a metal-induced unilateral crystallization technique, and is grain-enhanced further in a high temperature annealing step. Deep submicron fully self-aligned bottom-gate pMOS transistors with channel length less than 0.5 /spl mu/m are fabricated. The measured performance parameters include threshold voltage of -0.43 V, subthreshold swing of 113 mV/dec, effective hole mobility of 147 cm/sup 2//V-s, off-current of 0.17 pA//spl mu/m, and on-off current ratio of 7.1/spl times/10/sup 8/.     

An accurate two-dimensional numerical analysis of the MOS transistor

A two dimensional numerical analysis has been made for MOS transistors with both small and large values of channel lenghts and various bias conditions. Results are compared with a simplified analysis of the MOST and with experimental data obtained on devices. Detailed pictures of the free carriers density distribution and of the voltage distribution are presented for various channel lengths and two dimensional effects are clearly seen near the source and the drain that are very hardly accounted for in a simplified one dimensional analysis. Such a program seems to be a very powerful tool for device optimisation and physical understanding of the behaviour of very small devices used in complex circuits.     

Compact modeling of thermal noise in the MOS transistor

Although some of the recently proposed compact models for thermal noise in MOS transistors exhibit a good match with experimental data, we believe most of the existing compact models suffer from incorrect physical assumptions or modeling (e.g., absence of carrier heating, incorrect modeling of velocity saturation effect, wrong modeling of diffusivity, etc.). This brief presents a new, completely analytical thermal noise model based on consistent physical assumptions.     

Limitations of quasi-static capacitance models for the MOS transistor

This letter compares the Meyer [1] and Ward [2,3] quasi-static, intrinsic capacitance formulations for the MOS transistor to an exact, non-quasi-static, incremental analysis of a simplified device. This analysis yields an incremental admittance matrix for the device whose terms are ratios of power series. The Meyer and Ward models are shown to be approximations to this exact solution. Experimental admittance versus frequency data are presented which show good agreement with this theory. The high-frequency modeling of the Ward and Meyer formulations are compared to the data above, and the limitations of these models are discussed.     

Theory of the fully depleted SOS/MOS transistor

The subject of full film depletion of the SOS/MOS transistor and its impact on threshold voltage and the weak inversion slope factor is addressed. A rigorous one dimensional field analysis of the SOS transistor is performed. The silicon/sapphire interface is treated in the analysis as a discrete interface. The depletion approximation is invoked in order to obtain relatively simple expressions for threshold voltage and the weak inversion slope factor. Experimental data is then compared with data generated by the mathematical models. Both the experimental and model data indicate increase in both absolute threshold voltage and weak inversion slope factor with decreasing epitaxial film thickness.     

On the design of algorithms for VLSI systolic arrays

This paper is concerned with the mapping of cyclic loop algorithms into special-purpose VLSI arrays. The mapping procedure is based on the mathematical transformations of index sets and data dependence vectors. Necessary and sufficient conditions for the existence of valid transformations are given for algorithms with constant data dependences. Two examples of different algorithms are given to illustrate the proposed mapping procedure; first is the LU decomposition of a matrix which leads to constant data dependence vectors, and secondly is the dynamic programming which leads to dependences which are functions on the index set and are more difficult to be mapped into VLSI arrays.