Mixed-Mode BIST Using Embedded Processors

In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not completely random pattern testable, the test programs have to generate deterministic patterns after random testing. Usually the random test part of the program requires long run times whereas the part for deterministic testing has high memory requirements.In this paper it is shown that an appropriate selection of the random pattern test method can significantly reduce the memory requirements of the deterministic part. A new, highly efficient scheme for software-based random pattern testing is proposed, and it is shown how to extend the scheme for deterministic test pattern generation. The entire test scheme may also be used for implementing a scan based BIST in hardware.     

On Using Twisted-Ring Counters for Test Set Embedding in BIST

We present a novel built-in self-test (BIST) architecture for high-performance circuits. The proposed approach is especially suitable for embedding precomputed test sets for core-based systems since it does not require a structural model of the circuit, either for fault simulation or for test generation. It utilizes a twisted-ring counter (TRC) for test-per-clock BIST and is appropriate for high-performance designs because it does not add any mapping logic to critical functional paths. Test patterns are generated on-chip by carefully reseeding the TRC. We show that a small number of seeds is adequate for generating test sequences that embed complete test sets for the ISCAS benchmark circuits.Instead of being stored on-chip, the seed patterns can also be scanned in using a low-cost, slower tester. The seeds can be viewed as an encoded version of the test set that is stored in tester memory. This requires almost 10X less memory than compacted test sets obtained from ATPG programs. This allows us to effectively combine high-quality BIST with external testing using slow testers. As the cost of high-speed testers increases, methodologies that facilitate testing using slow testers become especially important. The proposed approach is a step in that direction.     

Test Cycle Count Reduction in a Parallel Scan BIST Environment

This paper describes a novel method that can be used to reduce test cycle count in a parallel access scan based Built-In-Self-Test (BIST) environment. An algorithm that allows the efficient application of deterministically generated patterns is proposed. This approach allows BIST fault coverage to be increased using deterministic vectors, while minimizing the cost, in terms of test cycles, of applying the vectors.     

Decentralized BIST Methodology for System Level Interconnects

This paper presents an architecture for the local generation of global test vectors for interconnects in a multiple scan chain environment. A unified BIST module is inserted as the gateway for each scan chain to transform the hierarchy of backplane, boards, and scan chains into a one-dimensional array of scan chains. The BIST modules are identical for all the scan chains except for the programmable personalized memories. The personalized memory contains a scan stage type table for the test generation, response compression, and driver contention avoidance. It also contains a scan chain identification number which serves as the seed for the generation of globally distinct serial vectors. The proposed methodology achieves 100% coverage on stuck-at and short faults.     

LFSR Reseeding-Oriented Low-Power Test-Compression Architecture for Scan Designs

Massive test data volume and excessive test power consumption have become two strict challenges for very large scale integrated circuit testing. In BIST architecture, the unspecified bits are randomly filled by LFSR reseeding-based test compression scheme, which produces enormous switching activities during circuit testing, thereby causing high test power consumption for scan design. To solve the above thorny problem, LFSR reseeding-oriented low-power test-compression architecture is developed, and an optimized encoding algorithm is involved in conjunction with any LFSR-reseeding scheme to effectively reduce test storage and power consumption, it includes test cube-based block processing, dividing into hold partition sets and updating hold partition sets. The main contributions is to decrease logic transitions in scan chains and reduce specified bit in test cubes generated via LFSR reseeding. Experimental results demonstrate that the proposed scheme achieves a high test compression efficiency than the existing methods while significantly reduces test power consumption with acceptable area overhead for most Benchmark circuits.     

并行折叠计数器的BIST方案

 本文提出了一种新的基于初始状态的并行折叠计数结构,并给出了建议的多扫描链的BIST方案.与国际上同类方法相比,该方案需要更少的测试数据存储容量、更短的测试应用时间,其平均测试应用时间是同类方案的0.265%,并且能很好地适用于传统的EDA设计流程.     

Deterministic BIST with Partial Scan

An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flipflops to be scannable so that the remaining circuit has a pipeline-like structure. Experiments show that scanning less flipflops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead.     

Application of Deterministic Logic BIST on Industrial Circuits

We present the application of a deterministic logic BIST scheme based on bit-flipping on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5–15%. It is demonstrated that a trade-off is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.     

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters

In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counter. Combined with classical approaches for test width compression and with pseudo-random pattern generation these new techniques provide an efficient and flexible solution for scan-based BIST. Experimental results show that the proposed scheme outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters.     

BIST TPG for Combinational Cluster Interconnect Testing at Board Level

A novel built-in self-test (BIST) architecture and a test pattern generator (TPG) design methodology to program this architecture are presented for inter-IC interconnects among combinational non-boundary scan ICs (often called cluster-ICs) via IEEE 1149.1 boundary scan architecture (BSA). Due to the expense and complexity of BSA circuitry, cluster-ICs are still widely used in modern circuit boards. Since combinational logic and 3-state cluster nets exist within cluster interconnect, in order to test all detectable faults in inter-IC nets that include cluster-ICs, newly identified TPG requirements are used to guarantee fault coverage during the design of proposed BIST architecture. This architecture contains a two-level C-TPG that generates constrained pseudo-random patterns for boundary scan cells (BSCs) of cluster control cones, a D-TPG that generates patterns for BSCs of cluster data cones, and a look-up table which is programmed to select, for each BSC, a specific C-TPG or D-TPG stage whose content is shifted into that BSC. This test architecture provides a true BIST solution for cluster testing. The proposed methodology generates TPGs that (i) guarantee the avoidance of multi-driver conflicts when testing via BSA, (ii) guarantee the detection of all testable interconnect faults, (iii) have low area overheads, and (iv) have short test lengths.     

BIST for network on chip communication infrastructure based on combination of extended IEEE 1149.1 and IEEE 1500 standards

In this paper we propose a BIST based method to test network on chip (NOC) communication infrastructure. The proposed method utilizes an IEEE 1149.1 architecture based on BIST to at-speed test of crosstalk faults for inter-switch links as well as an IEEE 1500-compliant wrapper to test switches themselves in NOC communication infrastructure. The former architecture includes enhanced cells intended for MAF model test patterns generation and analysis test responses, and the later architecture includes: (a) a March decoder which decodes and executes March commands, which are scanned in serially from input system, on First-In-First-Out (FIFO) buffers in the switch; and (b) a scan chain which is defined to test routing logic block of the switch.To at-speed test inter-switch links one new instruction is used to control cells and TPG controller. Two new instructions, as well as, are applied to activate March decoder and to control scan activities in switch test session. These instructions are defined to fully comply with conventional IEEE 1149.1 and IEEE 1500 standards.     

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test methodology, minor modifications should be applied to base processor within its test phase. That is, we modify the controller to interpret some of the instructions differently only within the initial test mode. In this paper, we have proposed a fuctional self-test methodology that is deterministic in nature. In our proposed architecture, a self test program called BIST Program is stored in an embedded ROM as a vehicle for applying tests. We first start with testing processor core using our proposed architedture. Once the testing of the processor core is completed, this core is used to test the embedded SRAMs. A test algorithm which utilizes a mixture of existing memory testing techniques and covers all important memory faults is presented in this paper. The proposed memory test algorithm covers 100% of the faults under the fault model plus a data retention test. The hardware overhead in the proposed architecture is shown to be negligible. This architecture is implemented on UTS-DSP (University of Tehran and Iran Communicaton Industries (SAMA)) IC which has been designed in VLSI Circuits and Systems Laboratory.     

Weighted pseudorandom hybrid BIST

This paper presents a new test data-compression scheme that is a hybrid approach between external testing and built-in self-test (BIST). The proposed approach is based on weighted pseudorandom testing and uses a novel approach for compressing and storing the weight sets. Three levels of compression are used to greatly reduce test costs. Experimental results show that the proposed scheme reduces tester storage requirements and tester bandwidth requirements by orders of magnitude compared to conventional external testing, but requires much less area overhead than a full BIST implementation providing the same fault coverage. No test points or any modifications are made to the function logic. The paper describes the proposed hybrid BIST architecture as well as two different ways of storing the weight sets, which are an integral part of this scheme.     

Deterministic BIST with Multiple Scan Chains

A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage.The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.     

一种高速增益单元存储器的内建自测试方案

介绍了一种用于测试高速增益单元嵌入式动态随机存储器的内建自测试方案。该方案包括了指令集设计和体系结构设计。四级指令流水线的引入使全速测试成为可能。该设计方案可以通过执行不同的测试指令,对待测存储器执行多种类型的测试,从而达到较高的故障覆盖率。该内建自测试模块被集成在了一个存储容量为8kb的增益单元嵌入式动态随机存储器芯片中,并在中芯国际0.13μm标准逻辑工艺下进行了流片验证。芯片测试结果表明,该内建自测试方案可以在多种测试模式下对待测存储器执行全速测试,提高了测试速度,降低了对自动测试设备的性能要求,提高了测试的效率。     

"龙腾"S2微处理器测试结构设计

介绍了"龙腾"52微处理器测试结构设计方法,详细讨论了采用全扫描测试、内建自测试(BIST)等可测性设计(DFT)技术.该处理器与PC104全兼容,设计中的所有寄存器采用全扫描结构,设计中的存储器采用内建自测试,整个设计使用JTAG作为测试接口.通过这些可测性设计,使芯片的故障覆盖率达到了100%,能够满足流片后测试需求.     

Minimized Power Consumption for Scan-Based BIST

Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture are analyzed, the modules and modes with the highest power consumption are identified, and design modifications to reduce power consumption are proposed. The design modifications include some gating logic for masking the scan path activity during shifting, and the synthesis of additional logic for suppressing random patterns which do not contribute to increase the fault coverage. These design changes reduce power consumption during BIST by several orders of magnitude, at very low cost in terms of area and performance.     

一种混合信号SoC中模数转换器的内建自测试方案

提出了一种针对混合信号SoC中ADC的动态参数与静态参数测试的内建自测试方案.由于动态参数和静态参数在同一个测试电路中都能够得到测试,因此能够更加全面准确地反映待测器件的性能.通过对存储器和计算资源的合理配置和复用,将两种测试的激励产生和响应分析集成在一起,最大程度地减少了对电路面积的影响.整个设计在FPGA上实现,实验结果证明了其可行性.     

一种新型低峰值功耗的BIST设计研究

随着手持设备的兴起和芯片对晶片测试的要求越来越高,内建自测试的功耗问题引起了越来越多人的关注。文章对目前内建自测试的可测性设计技术进行了分析,并提出了折叠种子优化降低节点峰值功耗的模型,通过调整种子结构和测试向量的相关性的办法来避免过高的SoC测试峰值功耗。采取了屏蔽无效测试模式生成、提高应用测试向量之间的相关性以及并行加载向量等综合手段来控制测试应用,使得测试时测试向量的输入跳变显著降低,从而大幅度降低节点的峰值功耗。实验结果表明,该方案可以有效地避免BIST并行执行可能带来的过高峰值功耗。     

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor

We present a test-per-clock BIST scheme using memory for storing test patterns that reduces the number of clock cycle necessary for testing. Thus, the test application time is shorter and energy consumption is lower than those in other solutions. The test hardware consists of a space compactor and a MISR, which provides zero error aliasing for modeled faults. The test pattern generator (TPG) scheme is based on a T-type flip-flop feedback shift register. The generator can be seeded similarly to a D-type flip-flop shift register. It generates test patterns in a test-per-clock mode. The TPG pattern sequence is modified at regular intervals by adding a modulo-2 bit from a modification sequence, which is stored in a memory. The memory can be either a ROM on the chip or a memory in the tester. The test patterns have both random and deterministic properties, which are advantageous for the final quality of the resulting test sequence. The number of bits stored in the memory, number of clock cycles, hardware overhead and the parameters of the resulting zero aliasing space compactor and MISR are given for the ISCAS benchmark circuits. The experiments demonstrate that the BIST scheme provides shorter test sequences than other methods while the hardware overhead and memory requirements are kept low.