A new phase-locked loop used in a frequency synthesizer

A well-known contradiction in phase-locked frequency synthesizer design is between frequency resolution, on the one hand, and bandwidth of the phase-locked loop (PLL), on the other. To solve this problem, a technique that uses an algorithm that produces a group of different divide numbers to the programmable feedback frequency divider of PLL for each required output frequency is presented. The interference frequency at the output of the phase detector of PLL and the frequency resolution can then be set independent of each other. High resolution and wide bandwidth are achieved simultaneously, with a simple synthesizer design leading to savings in power consumed and device cost     

Pulsed phase-locked loop calibration over frequency

This paper presents a method of correcting for unwanted phase shifts introduced by interchanging ultrasonic transducers and other measurement system components when using the pulsed phase-locked loop (PPLL) ultrasonic system. Theory is derived mathematically separating phase errors into their constituents. The relationship to a previously derived method of determining the number of periods into the tone-burst, at which the system samples, is established, and a method of adjusting this number to be an integer is presented. Implementation of the technology on a computer is demonstrated through experimental results on transducers of differing frequencies and diameters. Sensitivity to path-length is tested. This work has resulted in a straightforward means of calibrating transducers in conjunction with PPLL measurements using a single, fixed reference block     

A study on phase-noise reduction method in phase-locked loop systems

Experimental studies are carried out on phase noise and the correlation coefficient between the phase and average current noises of the voltage-controlled oscillator in phased-locked loop (PLL) systems. The precise phase stabilization technique is discussed, and new methods to reduce the phase noise are described in PLL systems, using the correlation.     

A multifunctional, reconfigurable pulse generator for high-frequency ultrasound imaging

High-frequency (>20 MHz) ultrasound (HFUS) imaging systems have made it possible to image small structures with fine spatial resolution. They find a variety of biomedical applications in dermatology, ophthalmology, intravascular imaging, and small-animal imaging. One critical technical challenge of HFUS is to generate high-voltage, high-frequency pulsed signals to effectively excite the transducer for a high SNR. This paper presents the development of a multifunctional, reconfigurable pulse generator for HFUS imaging. The pulse generator can produce a high-voltage unipolar pulse, a bipolar pulse, or arbitrary pulses for B-mode imaging, Doppler measurement, and modulated excitation imaging. The characteristics of the pulses, such as timing, waveform, and frequency are reconfigurable by a high-speed field-programmable gate array (FPGA). Customized software was developed to interface with the FPGA through a USB connector for pulse selection, and easy, flexible, real-time pulse management. The hardware was implemented in a compact, printed circuit board (PCB)-based scheme using state-of-the-art electronics for costeffectiveness and fully digital control. Testing results show that the unipolar pulse can reach over 165 Vpp with a 6-dB bandwidth of 70 MHz, and the bipolar pulse and arbitrary pulses can reach 150 and 60 Vpp with central frequencies of 60 and 120 MHz, respectively.     

A novel flash fast-locking digital phase-locked loop: design and simulations

A flash digital phase-locked loop (DPLL) is designed using 0.18 μm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz?2 GHz. The DPLL operation includes two stages: (i) a novel coarse-tuning stage based on a flash algorithm similar to the algorithm employed in flash A/D converters, and (ii) a fine-tuning stage similar to conventional DPLLs. The flash portion of the DPLL is made up of frequency comparators, an encoder and a decoder which drives a multiple charge pump (CP)/lowpass filter (LPF) combination. Design considerations of the flash DPLL circuit components as well as implementation using Cadence design tools are presented. Spectre simulations were also performed and demonstrated a significant improvement in the lock time of the flash DPLL as compared to the conventional DPLL. By increasing the number of frequency comparators, the lock time is expected to be always less than 100 ns in the above-mentioned frequency range.     

A 1.5 GHz phase-locked loop with leakage current suppression in 65 nm CMOS

In the nanoscale CMOS process, the problem of leakage current causes the performance of the analog circuits to degrade. The leakage current of a loop filter, which is realised by MOS capacitors, significantly degrades the jitter performance of a phase-locked loop. A leakage suppression circuit is presented by using a combination of switchable varactors and current sources to compensate the leakage of MOS capacitors in a loop filter. This PLL has been fabricated in a 65 nm CMOS process and the core area is 0.4 X 0.5 mm². With the leakage suppression circuit, the peak-to-peak jitter and the rms jitter are 43 and 5.36 ps, respectively.The power is 17 mW for a 1.2 V supply.     

Fringe pattern demodulation with a two-frame digital phase-locked loop algorithm

A novel technique called a two-frame digital phase-locked loop for fringe pattern demodulation is presented. In this scheme, two fringe patterns with different spatial carrier frequencies are grabbed for an object. A digital phase-locked loop algorithm tracks and demodulates the phase difference between both fringe patterns by employing the wrapped phase components of one of the fringe patterns as a reference to demodulate the second fringe pattern. The desired phase information can be extracted from the demodulated phase difference. We tested the algorithm experimentally using real fringe patterns. The technique is shown to be suitable for noncontact measurement of objects with rapid surface variations, and it outperforms the Fourier fringe analysis technique in this aspect. Phase maps produced withthis algorithm are noisy in comparison with phase maps generated with the Fourier fringe analysis technique.     

Real-time fringe pattern demodulation with a second-order digital phase-locked loop

The use of a second-order digital phase-locked loop (DPLL) to demodulate fringe patterns is presented. The second-order DPLL has better tracking ability and more noise immunity than the first-order loop. Consequently, the second-order DPLL is capable of demodulating a wider range of fringe patterns than the first-order DPLL. A basic analysis of the first- and the second-order loops is given, and a performance comparison between the first- and the second-order DPLL's in analyzing fringe patterns is presented. The implementation of the second-order loop in real time on a commercial parallel image processing system is described. Fringe patterns are grabbed and processed, and the resultant phase maps are displayed concurrently.     

Pulsed phase-locked loop technology improvements for greateraccuracy and expanded capabilities

This paper presents the design for a new pulsed phase-locked loop (PPLL) instrument. Earlier phase detection methods are analyzed for potential error sources, and an alternative phase detection method with fewer sources of error is described. This alternative method of phase detection is incorporated into a fully automated PPLL instrument. Data taken with the new system is compared to data taken with an earlier PPLL instrument. This comparison shows that the alternative phase detection does reduce error. The control loop is analyzed for stability and optimization, and a method of automating this optimization is presented. A method of wave-form acquisition using the automated PPLL that permits automatic location of the received echo is also described     

Fringe pattern demodulation with a two-dimensional digital phase-locked loop algorithm

A novel technique called a two-dimensional digital phase-locked loop (DPLL) for fringe pattern demodulation is presented. This algorithm is more suitable for demodulation of fringe patterns with varying phase in two directions than the existing DPLL techniques that assume that the phase of the fringe patterns varies only in one direction. The two-dimensional DPLL technique assumes that the phase of a fringe pattern is continuous in both directions and takes advantage of the phase continuity; consequently, the algorithm has better noise performance than the existing DPLL schemes. The two-dimensional DPLL algorithm is also suitable for demodulation of fringe patterns with low sampling rates, and it outperforms the Fourier fringe analysis technique in this aspect.     

大气激光应急通信系统中的锁相环设计

在传统锁相环的基础上,提出并设计了一种数字锁相环,其在大气激光应急通信系统中的功能是用输入信号预处理得到的准同步信号去同步当地时钟信号,使之相位保持一致。该数字锁相环采用闭环反馈跟踪方法,并用 CPLD 器件予以实现。在 MAX PLUSⅡ环境下的仿真试验表明,该锁相环锁相误差小、抖动小、可靠性高;与传统锁相环相比,该设计编程方便,工作可靠。     

Mutually connected phase-locked loop networks: dynamical models and design parameters

Distribution of timing signals is an essential factor for the development of digital systems for telecommunication networks, integrated circuits and manufacturing automation. Originally, this distribution was implemented by using the master?slave architecture with a precise master clock generator sending signals to phaselocked loops (PLL) working as slave oscillators. Nowadays, wireless networks with dynamical connectivity and the increase in size and operation frequency of the integrated circuits suggest that the distribution of clock signals could be more efficient if mutually connected architectures were used. Here, mutually connected PLL networks are studied and conditions for synchronous states existence are analytically derived, depending on individual node parameters and network connectivity, considering that the nodes are nonlinear oscillators with nonlinear coupling conditions. An expression for the network synchronisation frequency is obtained. The lock-in range and the transmission error bounds are analysed providing hints to the design of this kind of clock distribution system.     

水声通信中内嵌锁相环的格型均衡器

最小二乘格型（Least Squares Lattice,LSL）自适应均衡算法具有收敛速度快、算法复杂度低、对舍入误差不敏感等特点,适于应用在水下实时通信中。在LSL均衡算法的基础上,为增强对多普勒频移的跟踪能力,在均衡器中加入等效二阶锁相环（PLL）,提出了两种算法：后置PLL的LSL算法（LSL-PLL-post）和预置PLL的LSL算法（LSL-PLL-pre）。对RLS、LSL、LSL-PLL-post和LSL-PLL-pre四种算法进行了仿真,结果表明：PLL显著增强了LSL均衡器对多普勒频移的跟踪能力;在多径和多普勒环境下,LSL-PLL-pre是四种算法中性能最好的。湖试数据分析表明,LSL-PLL-pre算法性能略优于LSL-PLL-post算法,更具实用价值。     

集成锁相环在激光脉冲调制系统中的应用

锁相环由鉴相器、环路滤波器及压控震荡晶体组成,是一个能跟踪输入信号频率和相位的闭环自动控制系统。研制的激光脉冲调制系统采用锁相技术,以单片、集成锁相环代替分立元件,实现了片内鉴频和鉴相的功能。研制的腔倒空驱动器能够输出 4MHz, 800kHz, 400kHz, 80kHz,40kHz, 8kHz, 4kHz, 800Hz, 400Hz 等不同重复频率的脉冲信号,输出功率达到瓦级,满足了声光布拉格池的要求。该激光脉冲调制系统已经应用在皮秒时间相关单光子计数光谱仪系统中,取得了比较理想的效果。     

Instrumental implementation of a neuronlike generator with spiking and bursting dynamics based on a phase-locked loop

An instrumental model of a neuron based on a phase-locked loop with a bandpass filter in the control loop is proposed. The main constructive elements of the system are described. The existence of different dynamic modes that are qualitatively similar to the spiking and bursting neuron dynamics has been experimentally demonstrated.     

A high-frequency photometer

Translated from Izmeritel'naya Tekhnika, No. 12, pp. 30–31, December, 1992.     

Magnetic film phase-locked oscillator

The Phase-Locked Oscillator (PLO), also known as a parametron, was proposed almost simultaneously in 1954 by Von Neuman and Goto as a digital device [1], [2]. Since that time, much developmental of effort has been placed on parametrons utilizing ferrite cores and magnetic films. A comprehensive presentation of the use and application of the PLO can be found in the technical literature [3]-[8]. This paper is concerned with the mathematical analysis of the magnetic film PLO which is described by a nonlinear Mathieu equation. Although there are many analyses of the PLO, they all fall short of yielding a closed-form solution which quantitatively and explicitly relates circuit and film parameters to actual operation [2],[3],[7]-[12]. By establishing such a relationship, solutions for the transient response with limiting characteristics, operating frequency, and steady-state operation have been obtained.     

A high-temperature high-frequency pneumatic vibrostand

The design and operating principle of a high-frequency pneumatic vibrostand designed for resonant tests of turbomachinery blade-type parts and specimens in the form of rods and plates at high temperatures are described. It is noted that the stand is especially effective for testing elements of structures of composite materials.Translated from Problemy Prochnosti, No. 2, pp. 96–100, February, 1990.     

A morphology proposal in commercial-off-the-shelf reconfigurable machine tools

Global manufacturing is continuously facing changing demands, the unpredictable part family supply that a machine tool user has to deal with needs varying machine morphologies. The reconfigurable manufacturing system paradigm proposes the need for the right capacity, for the right demand with an economical ramp-up period. The machinist needs to have a systematic manner of configuring the machines, given a set of modules that will be configured and reconfigured for the various demands in the lifespan of a manufacturing system. In this article, the author proposes how the machinist can go about identifying the different morphologies in advance. The method is simple and user-friendly in consideration of the main users who may have basic skills being deficient in sophistication and complexity; it further assists in the determination of the capability the manufacturer has with the available modules.