质子引入的6T SRAM单粒子翻转截面预测模型

提出了一种基于SOI工艺6T SRAM单元质子辐射的单粒子饱和翻转截面的预测模型,该模型通过器件物理来模拟辐照效应,利用版图和工艺参数来预测质子引入的单粒子饱和翻转截面。该模型采用重离子的SPICE测试程序对质子辐射的翻转截面进行预测,该方法简单高效,测试实例表明在0.15μm SOI工艺下,预测的质子引入的单粒子翻转饱和截面和实际测试的翻转截面一致。     

温度对SRAM器件单粒子翻转重离子测试的影响

本文基于单粒子效应地面重离子模拟实验,选取体硅SRAM与SOI SRAM两种待测器件,在兰州重离子加速器上（HIRLF）研究了温度对单粒子翻转测试的影响。用12C粒子对体硅SRAM器件的温度实验显示,单粒子翻转截面易受温度的影响。对于SOI SRAM器件,12C粒子测得的单粒子翻转截面随温度升高有显著的增大,但209Bi 粒子测得的单粒子翻转截面却随温度保持恒定。用Monte Carlo的方法分析了温度对单粒子翻转测试的影响规律,发现在单粒子翻转阈值LET附近温度对单粒子翻转截面有大的影响,但是随着单粒子翻转的发生接近于饱和,单粒子翻转截面渐渐的表现出低的温度依赖性。基于该模拟结果,我们对实验数据进行了分析,同时提出了一种准确评估在轨翻转率的合理方法。     

基于激光背部辐照方法的小尺寸器件的单粒子效应特性

本文基于脉冲激光背部辐照试验方法,测试了小尺寸器件的单粒子翻转与闩锁特性,以克服高集成度器件日益增加的金属布线层对激光试验的影响。研究了SRAM器件存储的数据类型对器件单粒子翻转阈值与截面的影响特性。试验测试了深亚微米器件微闩锁效应的电流变化特征。建立了一种激光能量与重离子LET值对应关系的经验公式,用于评估小尺寸器件的等效激光LET值。此外,利用激光背部辐照试验方法,初步试验研究了90nmSOI工艺PowerPC微处理器的单粒子翻转特性。     

纳米器件质子在轨单粒子翻转率预计方法

研究了纳米器件在空间轨道中质子引起单粒子翻转(SEU)率的预计方法。以65 nm SRAM为样品,利用加速器进行了质子和重离子单粒子翻转试验,分别基于质子试验数据和重离子试验数据,预计了空间轨道中质子引起的单粒子翻转率。结果表明,用重离子试验数据预计的质子单粒子翻转率比用质子试验数据预计的低1.5个数量级。研究认为,为了评估纳米器件单粒子翻转敏感性,需进行质子单粒子翻转试验,并基于质子试验数据进行在轨质子翻转率预计。     

一种多模式SRAM单粒子试验系统的设计与实现

提出了一种基于NIOS II的异步SRAM单粒子效应检测系统,用于评估抗辐射加固SRAM电路的抗单粒子效应能力.该检测系统可以对异步SRAM进行四种工作模式下的动态和静态检测,利用该检测系统在重离子加速器上对一款异步SRAM进行了单粒子效应试验,获得了5种离子的试验数据,统计分析后得到了器件的单粒子翻转阈值、单粒子翻转饱和截面和单粒子翻转在轨错误率,并与国外同款电路进行了对比,最后依据试验结果给出了评估结论.     

SRAM激光微束单粒子效应实验研究

结合器件版图,通过对2 k SRAM存储单元和外围电路进行单粒子效应激光微束辐照,获得SRAM器件的单粒子翻转敏感区域,测定了不同敏感区域单粒子翻转的激光能量阈值和等效LET阈值,并对SRAM器件的单粒子闭锁敏感度进行测试.结果表明,存储单元中截止N管漏区、截止P管漏区、对应门控管漏区是单粒子翻转的敏感区域;实验中没有测到该器件发生单粒子闭锁现象,表明采用外延工艺以及源漏接触、版图布局调整等设计对器件抗单粒子闭锁加固是十分有效的.     

粒子入射条件对28nm SRAM单元单粒子电荷共享效应影响的TCAD仿真研究

利用器件仿真工具TCAD,建立28 nm体硅工艺器件的三维模型,研究了粒子入射条件和器件间距等因素对28 nm体硅工艺器件单粒子效应电荷共享的影响规律。结果表明,粒子LET值增大、入射角度的增大、器件间距的减小和浅槽隔离(STI)深度的减少都会增加相邻器件的电荷收集,增强电荷共享效应,影响器件敏感节点产生的瞬态电流大小;SRAM单元内不同敏感节点的翻转阈值不同,粒子LET值和入射角度的改变会对SRAM单元的单粒子翻转造成影响;LET值和粒子入射位置变化时,多个SRAM单元发生的单粒子多位翻转的位数和位置也会变化。     

FPGA刷新控制电路测试方法的研究

SRAM型现场可编程门阵列（FPGA）电路信号处理性能强大,在航天器中应用非常广泛。但SRAM型FPGA的逻辑单元在存在大量宇宙射线和高能粒子的空间环境中容易发生单元翻转现象,导致器件逻辑功能异常。通过刷新控制电路对FPGA的逻辑功能持续刷新,是当下解决单元翻转问题的通用方法。为了满足抗单粒子翻转的系统需求,FPGA刷新控制电路本身的抗单粒子翻转性能也需要通过一定的试验方法进行充分验证。设计了1种辐照试验测试方法,对FPGA刷新控制电路进行了辐照测试,通过该辐照方法系统地验证了该电路的抗单粒子翻转性能。     

基于Geant4的三维半导体器件单粒子效应仿真

在空间中,辐射粒子入射半导体器件,会在器件中淀积电荷.这些电荷被器件的敏感区域收集,造成存储器件(如静态随机存储器(SRAM))逻辑状态发生变化,产生单粒子翻转(SEU)效应.蒙特卡洛工具-Geant4能够针对上述物理过程进行计算机数值模拟,可以用于抗辐射器件的性能评估与优化.几何描述标示语言(GDML)能够在Geant4环境下对器件模型进行描述.通过使用GDML建立三维的器件结构模型,并使用Geant4进行不同能量质子入射三维器件模型的仿真.实验结果表明,在三维器件仿真中低能质子要比高能质子更容易引起器件的单粒子翻转效应.     

商用CMOS工艺SRAM脉冲中子辐射效应实验

为研究互补金属氧化物半导体(CMOS)工艺静态随机处理内存(SRAM)脉冲中子辐射效应机理,对SRAM翻转效应进行了蒙特卡罗模拟。该模拟基于脉冲中子辐照下SRAM翻转是单粒子翻转的叠加的假设,计算了单位翻转和伪多位翻转在总翻转数中的百分比。在西安脉冲反应堆上对3种特征尺寸商用SRAM开展了脉冲工况实验研究,得到了单位翻转和伪2位翻转数据,结合模拟结果分析了SRAM在脉冲中子作用下的翻转机制。     

SRAM single event upset calculation and test using protons in the secondary beam in the BEPC

The protons in the secondary beam in the Beijing Electron Positron Collider(BEPC) are first analyzed and a large proportion at the energy of 50-100 MeV supply a source gap of high energy protons.In this study, the proton energy spectrum of the secondary beam was obtained and a model for calculating the proton single event upset(SEU) cross section of a static random access memory(SRAM) cell has been presented in the BEPC secondary beam proton radiation environment.The proton SEU cross section for different characteristic dimensions has been calculated.The test of SRAM SEU cross sections has been designed,and a good linear relation between SEUs in SRAM and the fluence was found,which is evidence that an SEU has taken place in the SRAM.The SEU cross sections were measured in SRAM with different dimensions.The test result shows that the SEU cross section per bit will decrease with the decrease of the characteristic dimensions of the device,while the total SEU cross section still increases upon the increase of device capacity.The test data accords with the calculation results,so the high-energy proton SEU test on the proton beam in the BEPC secondary beam could be conducted.     

Single event upset and total dose radiation effects on rad-hard SRAMs

Radiation hardened 16K and 64K CMOS SRAMs were tested at the Brookhaven SEU Test Facility. No failures of 16K SRAMs were observed at room temperature with any value of the feedback resistors. SEU cross section measured at elevated temperatures was a function of reduced feedback resistance. A difference was observed in critical LET forBr andAu ions. SEU cross section decreased at very high angles of incidence. After initial SEU testing, the 64K SRAM was degraded by proton total dose irradiation. An increase in the SEU cross section as well as imprinting of the memory pattern was observed. Test chips fabricated by the same technology were also submitted to proton radiation. Threshold voltage shift was measured for NMOS transistors with and without inversion bias. An increase in the density of interface states for both NMOS and PMOS transistors was measured by the charge-pumping technique. This research has been supported by the NASA grants NAG-5-929 and NAG-9-333.     

Single Event Upset rate determination for 65 nm SRAM bit-cell in LEO radiation environments

The degradation of SRAM bit-cells designed in a 65 nm bulk CMOS technology in a Sun-Synchronous Low Earth Orbit (LEO) ionizing radiation environment is analyzed. We propose an inflight SEU rate estimation approach based on a modeled heavy ion cross section as opposed to the standard experimental characterization. Effects of irradiation with estimated LET spectrum in SRAM bit cell, i.e. the location of sensitive regions, its tendency to cause upset, magnitude and duration of transient current as well as voltage pulses were determined. It was found with SEU map that 65 nm SRAM bit-cell can flip even if high LET particle strikes in close proximity of bit-cell outside the SRAM bit-cell area. The SEU sensitive parameters required to predict SEU rate of on-board target device, i.e., 65 nm SRAM were calculated with typical aluminum spot shielding using fully physical mechanism simulation. In order to characterize the robustness of scaled CMOS devices, state of the art simulation tools such as Visual TCAD/Genius, GSEAT/Visual Particle, runSEU, were utilized whereas LEO radiation environment assessment, upset rate prediction was accomplished with the help of OMERE-TRAD software.     

One-Parameter Model for the Estimation of IC Susceptibility to Proton-Induced Single-Event Upsets

Singe-event upsets (SEUs) caused by high-energy protons are considered. An analytical model is proposed to represent the dependence of SEU cross section on proton energy. The model is based on a simple mechanism of proton-induced nuclear reactions in silicon. A computer simulation is conducted by the model. The results are found to agree with previous experiments. They indicate that the model enables one to predict susceptibility to proton-induced SEUs on the basis of a single value of SEU cross section measured at a proton energy higher than 100 MeV. It is shown that the approach may also work for heavy ions.     

驱动能力对SOI SRAM单元单粒子效应的影响仿真

采用silvaco软件对抗辐射不同沟道宽度的PD SOI NMOS器件单元进行了三维SEU仿真,将瞬态电流代入电路模拟软件HSPICE中进行SRAM存储单元单粒子翻转效应的电路模拟。通过这种电路模拟的方法,可以得到SRAM存储单元的LET阈值。通过对比LET阈值的实际测量值,验证了这种方法的实用性,并对不同驱动能力的SRAM单元进行了翻转效应的对比。在NMOS和PMOS驱动比相同的情况下,沟道宽度越大,SRAM的翻转LET阈值反而越高。     

Laser cross section measurement for the evaluation of single-event effects in integrated circuits

The cross section of ICs extracted from particles accelerator testing is extended to the pulsed laser testing. The extraction methodology attached to this new parameter is presented. It provides a new tool for integrated circuits reliability quantification, illustrated in the case of SEU sensitivity evaluation of a single SRAM cell.     

Memory-cell layout as a factor in the single-event-upset susceptibility of submicron dice CMOS SRAM

Computer simulations with the Spectre circuit simulator from Cadence Design Systems and a proton-accelerator experiment are conducted to investigate the relationship of single-event-upset (SEU) susceptibility to memory-cell layout in the context of a 0.18-μm CMOS SRAM using the dual interlocked storage cell (DICE) technology with differing separations of the pair transistors designed to store a 0 or 1, namely, 0.9 and 2.5 μm, respectively. The simulated values of critical charge for an upset are found to be greater by a factor of 10 for the wider separation. With 1-GeV proton irradiation, using the wider separation of pair transistors is found to reduce the SEU count by a factor of 5.5–15 (depending on the supply voltage). In the experiment, lowering the supply voltage of the memory bank from 1.8 to 0.7 V is found to increase on average the SEU cross section by a factor of 3. Close agreement is observed between the simulated and measured results.