一种混合信号集成电路衬底耦合噪声分析方法

讨论分析了混合信号集成电路衬底噪声耦合的机理,及对模拟电路性能的影响。提出了一种混合信号集成电路衬底耦合噪声分析方法,基于TSMC 0.35μm 2P4M CMOS工艺,以14位高速电流舵D/A转换器为例,给出了混合信号集成电路衬底耦合噪声分析方法的仿真结果,并与实际测试结果进行比较,证实了分析方法的可信性。     

深亚微米CMOS混合信号电路衬底噪声耦合宏模型

提出了一种基于二维器件模拟的深亚微米工艺外延型衬底的电阻宏模型.该宏模型通过器件模拟与非线性拟合相结合的方法建立,使衬底寄生参数的提取更加方便,同时保障了深亚微米电路特性的模拟精度.此外,该宏模型结构简单,可以得到与器件模拟基本一致的模拟结果,并可以方便地嵌入SPICE中进行一定规模的电路模拟.     

Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs

A synthesized compact modeling (SCM) approach for substrate coupling analysis is presented. The SCM is formulated using a scalable$Z$matrix approach for heavily doped substrates with a lightly doped epitaxial layer and using a nodal lumped resistance approach for lightly doped substrates. The SCM models require a set of process-dependent fitting coefficients and incorporate geometrical parameters of the substrate ports in a compact form that includes size, perimeter, and separation defined using the geometric mean distance to accommodate both far-field and near-field effects. The SCM approach is verified based on measurement data from two test chips, one in a custom lightly doped process and the other one using a 0.18-$muhbox m$BiCMOS lightly doped foundry process. The model accuracy is shown to be within 15% compared to measured data extracted from the test patterns. The SCM is exploited with application examples to show substrate model generation efficiency and accuracy at different levels of complexity, including a full chip substrate noise distribution analysis for a 2 mm by 2 mm chip with 319 substrate contacts.     

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

A methodology is proposed to efficiently analyze substrate noise coupled to a sensitive block due to an aggressor digital block in large-scale mixed-signal circuits. The methodology is based on identifying voltage domains on the substrate by exploiting the small spatial voltage differences on the ground distribution network of the aggressor circuit. Specifically, similarly biased regions on the substrate short-circuited by the ground network are determined, and each of these regions is represented by a single equivalent input port to the substrate. The remaining ports within that domain are ignored to reduce the computational complexity of the extraction process. An algorithm with linear time complexity is proposed to merge those substrate contacts exhibiting a voltage difference smaller than a specified value, identifying a voltage domain. An equivalent contact is placed at the geometric mean of the merged contacts, ignoring all of the remaining ports such as the source/drain junctions of the devices. The ground network impedance is updated for each merged contact based on the proposed algorithm to maintain sufficient accuracy of the noise voltage. The substrate with reduced input ports is extracted using an existing extraction tool to analyze the noise at the sense node. As compared to the full extraction of an aggressor circuit, the methodology achieves a reduction of more than four orders of magnitude in the number of extracted substrate resistors with a peak-to-peak error of 24%.     

一种离散点式IC衬底噪声有源抵消方法

在混合信号集成电路中,衬底耦合噪声是一个很大的问题.文章在现有噪声有源抵消电路的基础上,提出了一种新的多抵消点离散式有源噪声抵消方法.它采用有源放大器,产生负相噪声,通过若干个离散抵消点输出,与原来噪声相叠加、互相抵消,起到削弱噪声影响的作用.与原有噪声抵消电路相比,这种多抵消点离散式电路能更为显著地减小通过衬底传导的耦合噪声对模拟电路的影响,噪声幅度削减50%.     

重掺杂型混合信号集成电路衬底的噪声模型研究

应用器件模拟软件SILVACO模拟三种结构重掺杂型衬底中注入高频电流的分布,根据模拟结果分析得出重掺杂型衬底的简化模型为一单节点,进而将简化模型与实际的混合信号集成电路结合,建立起重掺杂型衬底的噪声模型,并给出了参数估算式。     

Placement of Substrate Contacts to Minimize Substrate Noise in Mixed-Signal Integrated Circuits

The placement of substrate contacts in epi and non-epi technologies is analyzed in order to control and reduce the substrate noise amplitude and spreading. The choice of small or large substrate contacts or rings for each of the two major technologies is highlighted. Design guidelines for placing substrate contacts so as to improve the noise immunity of digital circuits in mixed-signal smart-power systems are also presented.     

衬底耦合噪声的测量与分析

提出了一种测量衬底耦合噪声的新型电路结构，为了能够将耦合器声放大到方便于片外测量的幅度，采用了数字预校正技术，在测量工作真正开始之前就基本消除每一级运放的输入失调。并基于这项技术用0．6μmCMOS工艺实现了一块芯片，以衡量不同的离措施对于降低耦合效应有效程度。采用这项技术，仅用普遍的低精度（8－bit)示波器就可以完成对底耦合噪声的测量。     

边界元法在数模混合集成电路衬底耦合参数提取中的应用

把边界元方法运用到数模混合集成电路衬底耦合电阻参数的提取.求出了满足衬底边界条件的格林函数,而不是采用三维自由空间的格林函数,从而使需离散的边界仅仅是衬底表面的端口区.在计算阻抗元素时,利用基于快速富立叶变换(FFT)的离散余弦变换(DCT)使计算速度大大提高.和有限差分法相比,精度差不多而计算速度提高一个数量级以上.计算精度比Wemple采用解析方法计算有很大的提高.     

边界元法在数模混合集成电路衬底耦合参数提取中的应用

把边界元方法运用到数模混合集成电路衬底耦合电阻参数的提取.求出了满足衬底边界条件的格林函数,而不是采用三维自由空间的格林函数,从而使需离散的边界仅仅是衬底表面的端口区.在计算阻抗元素时,利用基于快速富立叶变换(FFT)的离散余弦变换(DCT)使计算速度大大提高.和有限差分法相比,精度差不多而计算速度提高一个数量级以上.计算精度比Wemple采用解析方法计算有很大的提高     

一种数模混合集成电路衬底耦合参数快速提取算法

边界元方法在计算衬底耦合电阻时，需要直接求解稠密矩阵方程Х＝Ｚ．Ｉ，时间复杂度为Ｏ（Ｎ＾３），Ｎ是总的衬底端口单元数，使得能计算的电路规模受到很大的限制。根据阻抗矩阵Ｘ中元素的物理意义，采用分段曲线拟合的方法。把它很好地表示成距离倒数的项式形式。在此基础上，采用多极点ＧＭＲＥＳ算法迅速求解Х＝Ｚ．Ｉ矩阵方程。时间复杂度为Ｏ（Ｎ），而结果和直接求解的结果非常接近。     

混合信号SoC中的衬底噪声耦合效应

衬底噪声耦合是深亚微米混合信号集成电路中常见的噪声干扰效应,严重地影响了模拟电路的性能。系统地阐述混合信号SoC中的衬底噪声耦合效应及其研究现状,讨论利用基于格林方程的边界元法对衬底建模的方法,并且分别从工艺、版图、电路等不同层次衬底噪声耦合效应的抑制方法与技术,同时对将来衬底噪声研究的发展方向以及新思路进行分析与讨论。     

单片数字锁相环衬底噪声的SPICE模拟及分析

应用PSPICE及采用C语言自编的外部程序,对单片数字锁相环中衬底噪声耦合及衬底噪声对电路性能的影响进行了模拟和分析,有助于进一步理解衬底噪声以及衬底噪声对复杂的混合信号电路工作的影响。提出了实际应用中据此选择合适的衬底类型和相应的减小衬底噪声的方法。     

混合信号芯片设计处理关键的转折阶段

通过简单地剪切和粘贴知识产权(IP)内核可以加快无工厂半导体公司的系统级芯片(SOC)设计。 过去十年中,涌现出大量的为系统制造商提供专用芯片(ASIC)的小型IC设计公司。这些被称为无工厂企业(因为他们将IC制造过程转交给商业芯片制造工厂),需要的启动资金较少,而且如果市场接受他们的产品的话,能够获得丰厚的回报。在大量设计工具的支持下,这些无工厂设计企业在历史悠久的大型芯片制造商,如IBM、Intel、Motorola和德州仪器公司所主导的市场中赢得了一席之地。     

Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs

In this paper, we introduce a novel substrate noise estimation technique during early floorplanning for mixed signal system-on-chip (SOC), based on block preference directed graph (BPDG). Given a set of analog and digital blocks, BPDG is constructed based on their inherent noise characteristics to capture the preferred relative locations for substrate noise minimization. For each instance of floorplan in sequence pair or ${B}^{ast}$-tree, we efficiently count the number of violations against BPDG which correlates remarkably well with accurate but computation-intensive substrate noise modeling. Thus, our BPDG-based model can guide fast substrate noise-aware floorplanning and layout optimization for mixed signal SOC. Our experimental results show that the proposed approach is significantly faster than conventional full-blown substrate model-based floorplanning.      

一种CMOS混合信号电路衬底噪声耦合模型

利用二维器件模拟器MEDICI提取出重掺杂外延型衬底的电阻宏简化模型,所需的6个参数均可通过器件模拟得到,能够精确表征混合信号集成电路中的衬底噪声特性。基于0.25μm CMOS工艺所建立的电阻宏模型,设计了简单的混合信号电路进行应用验证,证明了该模型能够有效表征混合信号集成电路的衬底噪声。     

Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog

Nowadays, the semiconductor industry directs its attention to mixed-signal System-on-Chip (SoC) applications. Main targets are the creation of accurate and fast mixed-signal SoC designs, composed of both digital and analog components, and the reduction of time to market for this kind of integrated circuits (ICs). In order to bring a mixed-signal SoC faster to the market, higher system-level simulation speed is required, with respect to traditional modeling approaches. Real Number Modelling (RNM) could be an effective solution. In this work, a sigma-delta analog-to-digital converter (ADC), a voltage-controlled oscillator (VCO) and a digital phase-locked loop (PLL) are implemented as real number models using SystemVerilog. This paper is an extended version of work previously published by the authors. Herein, more accurate and parameterizable models were created, while their validation process is analyzed and achieved using a novel metric for accuracy estimation. The proposed models’ parameterizability enhances the usability of the models to various SoC designs. Aim of this work is to underline the RNM effectiveness provided by SystemVerilog, and exhibit a way to apply RNM for modeling and simulation of widely used analog/mixed-signal (AMS) blocks. The presented real number models were compared to Verilog-A, Verilog-AMS, and transistor-level SPICE models. All tests showed that the proposed real number models based on SystemVerilog demonstrate noteworthy improvement on simulation efficiency, with respect to previous works in the literature, preserving simultaneously sufficient accuracy.

     

Impact of Substrate Digital Noise Coupling on the High-Frequency Noise Performance of RF MOSFETs

The impact of digital noise coupling through the substrate on RF MOSFETs was investigated in terms of the noise figure (NF) of the device up to 26.5 GHz. Previous works on the substrate digital noise coupling have treated the effect mostly in terms of the electrical isolation between ports, rather than actual devices, which does not provide direct information on the degradation of actual device performance parameters from such coupling. In this work, an actual NMOSFET was employed for test and the effect was described in terms of NF, a practical device performance parameter. The results show that NF is significantly degraded as the device enters the weak inversion state and/or $V_{rm ds}$ becomes smaller, suggesting a trade-off between low power operation and immunity against the substrate noise coupling. Also, it is experimentally verified that devices with a dual guard ring showed much smaller NF than those with a single guard ring.      

模拟/数字混合信号电路技术发展动态

叙述了国内外模拟和数字混合信号电路发展现状,重点讨论了国内外高性能模拟、射频电路、DSP、A/D转换器和SOC等器件研发和应用的一些情况,指出了这些器件在数模混合信号电路技术发展进程中的作用.