Si衬底上MBE GaAs MESFET与IC制备

叙述在MBE(分子束外延)GaAs/Si材料上制作GaAs MESFET与Ic的研究。考虑到GaAsIC与Si IC单片集成的需要,采用了Ti/TiW/Au肖特基金属化和Ni/AuGe/Ni/Au欧姆接触金属化,层间介质采用等离子增强淀积氮化硅和聚酰亚胺复合材料。在该工艺基础上,制备了性能良好的GaAs/Si MESFET与IC。     

Si和GaAs衬底上生成WN_x薄膜(英文)

WNx films with different composition are formed on Si(100) and GaAs (100) by the reactive rf sputtering in a mixed nitrogen-argon gas to study the influence of various conditions upon WNx film,- one of the most promising materials for self-aligned GaAs MESFET. With the increase of the partial pressure ratio of nitrogen gas or the decrease of sputtering pressure, the deposition rate of WNx film decreases and the atomic percentage of N in the film increaces until it is saturated. Annealing at high temperature in flowing H2 gas induces the decreace of atomic percentage of N in WNx film. After annealing at 900℃ for 30 minites in flowing N2 gas, WNx film formed at lower sputtering pressure is found to have W and W2N, and to have W, WN and/or W2N phase at a higher sputtering pressure. AES analysis shows no conspicuous diffusion after annealing. The electrical resisti vity of WNx film decreases by about 75% as compared with that of as-sputtered film.     

MBE GaAs/Si材料应力性质的研究

用光致发光谱及高分辨率的X射线双晶衍射对 MBE GaAs/Si异质结材料进行研究,发现GaAs外延层和Si衬底存在一定的晶向偏离,整个GaAs外延层呈现双轴张应力,这是GaAs和Si的晶格失配导致的双轴压应力和热膨胀系数失配导致的双轴张应力的总结果.本文根据一定的物理假设,推导出GaAs外延层中的平均应力,表明应力与材料所处的温度相关.据此,本文进一步用光致发光谱测量了25K至 260K温度范围内的应力,发现应力随温度的增大而下降,与理论公式反映的规律吻合.     

Si衬底上做GaAs电路

<正> 对于GaAs电路来说,主要障碍在于集成度。虽然GaAs电路速度要比Si集成电路的快得多,但成本却很高。一个4英寸的Si片只需5～10美元,而一个3英寸的GaAs片却需200～300美元。如果把GaAs电路试做在Si衬底上,不仅Si衬底的强度好,导热性好,而且成本也大大下降,但是电路的速度变慢了。在Si衬底上生长GaAs薄膜的主要难题就是要把两种物质的不同的晶体结构合在一起。因此,现在科学家们正在研究。如果这个难题一旦解决, 那么速度既快,价格又便宜的GaAs集成电路     

Si衬底上生长GaAs的技术

最近国外成功地用分子束外延法在Si衬底上生长出高质量的GaAs多晶.他们在3英寸Si衬底上研制出基极调制掺杂GaAs FETs(MODFETs),MESFETs和异质结双极晶体管,还成功地利用这项技术将SiMOSFETs与GaAsMESFETs进行集成.用Si作衬底生长的GaAs MESFETs跨导及夹断电压等性能均好于在GaAs衬底上制造的器件性能.     

刻槽Si衬底上GaAs微结构研究

本文介绍在刻楷Si衬底上用分子束外延嵌入生长GaAs的异质共平面技术。用横截面透射电子显微镜对槽壁非平面异质结的生长行为和微结构进行了研究,结果表明:槽壁的几何因素对外延层的成核行为和生长行为有一定影响,和Si[001]晶面相比,Si[113]可能是一个有利于半导体异质结生长的晶面。     

Si衬底上汽相生长GaAs获重大突破

<正> 由于硅具有高热导、良好的机械强度、高完整性及低廉的价格;发展GaAs/Si异质外延技术对于开拓Si集成和GaAs集成兼容电路有着宽广的应用前景。所以,在非极性半导体Si单晶上外延生长极性半导体GaAs单晶薄膜成为国际上最引入注目的研究课题之一。 文献中报道了许多异质外延GaAs/Si方面的研究工作,那是用MBE和MOCVD技术进行的。还有学者强调,异质外延GaAs/Si的唯一限制是必须采用MBE系统。     

Si(111)衬底上GaN外延材料的应力分析

对Si(111)衬底上GaN外延材料的应力随着低温AlN插入层数的变化进行了分析研究。通过喇曼散射谱在高频E2(TO)模式下的测试分析发现,随着低温AlN插入层数的增加,GaN材料的E2(TO)峰位逐渐接近体GaN材料的E2(TO)峰位(无应力体GaN材料的E2(TO)峰位为568cm-1),计算得出GaN材料的应力从1.09GPa减小到0.42GPa。同时,使用室温光荧光谱进行了分析验证。结果表明,Si衬底上GaN外延材料受到的是张应力,通过低温AlN插入层技术可以有效降低GaN材料的应力,并且最终实现了表面光亮的厚层无裂纹GaN材料。     

Photoreflectance Spectroscopy Study of LT-GaAs Layers Grown on Si and GaAs Substrates

The mechanical strains and densities of surface charge states in GaAs layers grown by low-temperature (LT) molecular-beam epitaxy on Si(100) and GaAs(100) substrates are investigated by photoreflectance spectroscopy. Lines corresponding to the fundamental transition (E _g ) and the transition between the conduction band and spin-orbit-split valence subband (E _g + Δ _SO ) in GaAs are observed in the photoreflectance spectra of Si/LT-GaAs structures at 1.37 and 1.82 eV, respectively. They are shifted to lower and higher energies, respectively, relative to the corresponding lines in GaAs/LT-GaAs structures. Comparing the spectra of the Si/LT-GaAs and GaAs/LT-GaAs structures, it is possible to estimate mechanical strains in LT-GaAs layers grown on Si (by analyzing the spectral-line shifts) and the density of charge-carrier states at the GaAs/Si heterointerface (by analyzing the period of Franz–Keldysh oscillations).     

GaAs/GaP Quantum-Well Heterostructures Grown on Si Substrates

Semiconductors - Molecular-beam epitaxy is used to produce GaP/Si hybrid substrates that allow the growth of highly efficient light-emitting heterostructures with GaAs/GaP quantum wells. Despite...     

在Si(211)衬底上分子束外延CdTe的晶格应变

文章利用高分辨率X射线衍射技术对分子束外延CdTe（211）B/Si（211）材料的CdTe外延薄膜进行了倒易点二维扫描,并通过获得的对称衍射面和非对称衍射面的倒易空间图,对CdTe外延层的剪切应变和正应变状况进行了分析.研究发现,对于CdTe/Si结构,随着CdTe厚度的增加,[1-1-1]、[01-1]两个方向的剪切角γ[1-1-1]和λ[01-1]都有变小的趋势,且γ[1-1-1]的大小约为γ[01-1]的两倍;对于CdTe/ZnTe/Si,ZnTe缓冲层的引入可以有效地降低CdTe层的剪切应变.CdTe层的正应变表现为张应变,主要来源于CdTe和Si的热膨胀系数存在差异,而在从生长温度280℃降至室温20℃的过程产生的热应变.     

Si表面制备GaAs单晶薄膜的反相畴消除

极性半导体GaAs在非极性半导体Si表面外延生长,普遍选用(100)面Si材料作衬底,外延时由于Ga,As原子占据不合适的晶格位置,通常导致结构缺陷--反相畴产生,而选用(100)面偏向[011]方向4°或(211)面的Si作衬底,可以有效消除反相畴.     

MBE高掺杂n-GaAs:Si和p-GaAs:Be的光致发光谱

我们对MBE高掺杂的n-GaAs∶Si和p-GaAs∶Be进行了光致发光研究,详细比较了高掺杂n-GaAs和p-GaAs在光谱线型,峰值半宽,峰值位置等方面的差异,以及两者的发光与温度的关系.由分析得出,对于高掺杂的n-GaAs,填充在导带内较高能态(K≠0)的电子与价带顶(K=0)空穴的非竖直跃迁是主要的发光过程.而对于高掺杂的p-GaAs,则是以导带底附近(K(?)0)的电子和价带顶附近(K(?)0)的空穴竖直跃迁为主要发光过程.     

GaAs基GaSb体材料及InAs/GaSb超晶格材料的MBE生长

采用分子束外延方法在GaAs(100)衬底上生长GaSb体材料,以此GaSb为缓冲层生长了不同InAs厚度的InAs/GaSb超晶格,其10K光致发光谱峰值波长在2.0～2.6 μm.高分辨透射电子显微镜观察证实超晶格界面清晰,周期完整.     

GaAs基GaSb体材料及InAs/GaSb超晶格材料的MBE生长

采用分子束外延方法在GaAs(100)衬底上生长GaSb体材料,以此GaSb为缓冲层生长了不同InAs厚度的InAs/GaSb超晶格,其10K光致发光谱峰值波长在2.0～2.6 μm.高分辨透射电子显微镜观察证实超晶格界面清晰,周期完整.     

Postgrowth Annealing of CdTe Layers Grown on Si Substrates by Metalorganic Vapor-Phase Epitaxy

Annealing conditions of CdTe layers grown on Si substrates by metalorganic vapor-phase epitaxy were studied. Typically, 3-μm-thick n-type (211) CdTe layers were annealed for 60 s in flowing hydrogen at atmospheric pressure by covering their surfaces with bulk CdTe wafers. At annealing temperatures above 700°C, improvement of crystal quality was confirmed from full-width at half-maximum values of double-crystal rocking-curve measurements and x-ray diffraction measurements. Photoluminescence measurements revealed no deterioration of electrical properties in the annealed n-CdTe layers. Furthermore, annealing at 900°C improved the performance of radiation detectors with structure of p-like CdTe/n-CdTe/n ⁺-Si substrate.     

ZnCdTe衬底上HgCdTe分子束外延的位错密度

报道了用 MBE的方法 ,在 Zn Cd Te衬底上制备 Hg Cd Te薄膜的位错密度研究结果。研究发现Hg Cd Te材料的位错密度与 Zn Cd Te衬底的表面晶体损伤、Hg Cd Te生长条件以及材料组分密切相关。通过衬底制备以及生长条件的优化 ,在 Zn Cd Te衬底上生长的长波 Hg Cd Te材料 EPD平均值达到 4.2× 1 0 5cm- 2 ,标准差为 3 .5× 1 0 5cm- 2 ,接近 Zn Cd Te衬底的位错极限。可重复性良好 ,材料位错合格率为 73 .7%。可以满足高性能Hg Cd Te焦平面探测器对材料位错密度的要求     

Electrical Properties of Halogen-Doped CdTe Layers on Si Substrates Grown by Metalorganic Vapor-Phase Epitaxy

Electrical properties of halogen-doped CdTe layers grown on Si substrates using iodine and chlorine dopants are presented. No change in electrical properties of the layers was observed with chlorine as a dopant. However, doping with iodine resulted in highly conductive n-type layers or highly resistive p-type layers depending upon the growth conditions, even though a similar amount of dopant was introduced into the growth chamber. Layers grown at 560°C, with a vapor-phase Te/Cd precursor ratio of 3.0, were p-type. The resistivity of the layers remained unchanged for low dopant supply rates, but increased abruptly when the dopant supply rate was increased beyond a certain value. On the other hand, layers grown at 325°C with Te/Cd ratios from 0.1 to 0.25 were n-type. A maximum free electron concentration of 1.3 × 10¹⁷ cm⁻³ was obtained at room temperature. The types and conductivities of the grown layers were strongly dependent on the growth conditions.