A polycide gate electrode with a conductive diffusion barrierformed with ECR nitrogen plasma for dual gate CMOS

A simple diffusion barrier technology for polycide gate electrodes is presented. An extremely thin silicon nitride layer is formed by poly Si surface nitridation with ECR nitrogen plasma of only nitrogen gas and without substrate heating. The silicon nitride layer acts as an excellent barrier to impurity diffusion from polysilicon to silicide. It was found that barrier formation with ECR nitrogen plasma results in no fatal degradation in the MOS interface characteristics. This technology is very effective for making dual polycide gates inexpensively due to its simplicity and a good affinity with conventional ULSI fabrication processes     

TiOx层在Pt/Ti电极中对Ti扩散的抑制作用

采用直流磁控溅射方法在SiO2/Si衬底上制备出Pt/Ti和Pt/TiOx底电极。用XRD分析其晶相结构,用AFM测量其晶粒尺寸和表面粗糙度。结果表明,用TiOx层代替金属Ti后,能有效地抑制在高温环境下Ti原子向Pt层扩散,使电极表面粗糙度减小(粗糙度为2.99 nm)。     

Silicide application on gated single-crystal, polycrystalline andamorphous silicon FEAs. II. Co silicide

For pt. I see ibid., vol.48, no.1, p.149-54 (Jan. 2001). For enhancement and stabilization of electron emission, Co silicides were formed from Co, Co/Ti and Ti/Co layers on silicon FEAs. Since Ti prevents oxygen adsorption on the Co film during silicidation, uniform and smooth Co silicide layers can be obtained by depositing Co first and then Ti on silicon tips, followed by rapid annealing. Among Co silicide FEAs, Co silicide formed from Ti/Co bi-layers shows the lowest leakage current, the highest failure voltage over 152 V and the largest anode current over 1 mA at the gate voltage of 150 V. Compared with silicon field emitters, the silicide FEAs formed from Ti/Co layers exhibited a significant improvement in maximum emission current, emission current fluctuation and stability, and failure voltage     

Thermal degeneration of Mo and Pt silicon Schottky diodes

In order to gain thermal stability and process compatibility, Mo and Pt silicon Schottky diodes have been annealed in an hydrogen atmosphere. A clear degeneration of the rectifying characteristics has been observed upon 450°C for Mo and 650°C for Pt.Although metal or defect diffusion could not be detected by transient capacitance measurements, the annealed devices did show anomalously high currents at low bias and at low temperatures. This excess current can be tentatively explained in terms of resonant tunnelling via deep centers near the interface metal-semiconductor induced by the annealing.The difference in the critical temperature for degeneration has its origin in the different behaviour of both barrier metals with silicon. While, in the case of platinum it seems that the silicide formation takes place at temperatures below 650°C with a subsequent diffusion of platinum or silicon vacancies into the silicon, in the case of molybdenum, the defect or metallic difusion apparently occurs before the silicide formation.     

The effect of Ti:W barrier metal on characteristics of palladium-silicide Schottky barrier diodes

The values of diode-quality factor and reverse-current leakage of Au/Pd/Ti:W/Pd₂Si/nSi unguarded Schottky barrier diodes are much higher than expected from silicide/silicon junction-radius induced highfield effects. Experimental Ti-, W-, and Ti:W-MIS structures were built and tested to show that Ti is responsible for the formation of a parasitic Ti-MIS structure around the unguarded-diode perimeter. This parasitic structure is responsible for excessive current leakage and also for an additional unguarded-diode degradation induced by annealing at 400 °C.     

Ti,W,Mo,TiW膜的阻挡性能比较

介绍了Ｔｉ－Ａｕ，Ｔｉ－Ｗ－Ｐｔ－Ａｕ，Ｍｏ－Ａｕ，ＴｉＷ－Ａｕ，ＴｉＷ－Ｐｔ－Ａｕ等多种金属膜分别在４００，４２５，４５０，４７５和５００℃，３０分钟等时退火后的显微镜观察结果和典型样品的俄歇能谱分析结果。结果表明，Ｔｉ由于在Ａｕ中扩散太快，阻挡性能较差，而Ｗ，Ｍｏ，ＴｉＷ都有较好的阻挡性能。结合实际应用，ＴｉＷ－Ｐｔ－Ａｕ应是硅微波功率管的金属化的较佳选择。     

Characterization of pulsed laser deposited Ba0.6Sr0.4TiO3 on Pt-coated silicon substrates

The high dielectric constant (Ba,Sr)TiO₃ (BST) films have been widely used to realize capacitors integrated on silicon with a high value of capacitance. The multilayer Pt/Ti/SiO₂/Si is one of the most currently used bottom electrodes for the integration of BST on silicon. However, the crystal orientation and the dielectric properties of ferroelectric thin films are greatly influenced by the underlying Pt/Ti metallization, and particularly by the out-diffusion of titanium towards the platinum surface during thermal treatments. In this study, we show that the heating stage of the Pt/Ti/SiO₂/Si substrate before the BST pulsed laser deposition is of primary importance in both favoring the (1 1 1) growth of the BST material within a wide range of oxygen deposition pressure and in reducing drastically the loss tangent values of Al/BST/Pt capacitors because of the oxygen saturation of platinum. Electrical measurements indicate the existence of an interfacial layer degrading the capacitance. They support the presence of an interfacial depleted layer. The dramatic increase of the loss tangent under positive polarities applied on the platinum electrode is attributed to the ohmic contact of the BST/Al interface. Except this increase, all of the electrical properties are very promising in view to realize capacitors with high capacitance value and low dispersion.     

Al/W/TiNx/TiSiy/Si barrier technology for1.0-μm contacts

A reliable contact diffusion barrier has been successfully formed by sintering in nitrogen a physically sputtered W/Ti bilayer. After a 650°C furnace anneal, a TiN_x/TiSi_y layer on contact with the silicon substrate was formed beneath the overlying W. No reaction between N₂ and W was observed. Arsenic implanted in the silicon substrate tended to retard the silicidation of titanium. Substantial redistribution of both B and As across the silicide layer was also observed during the contact sintering process. The 1.0-μ contacts fabricated with the Al/W/TiN_x/TiSi_y/Si barrier technology exhibited low and tightly distributed contact resistivities (less than 10^-6 Ω-cm²). No excessive leakage of the shallow junctions was observed even after thermally stressing the sample at 400°C for 8 h     

Titanium silicide/germanide formation on submicron features for high mobility SiGe channel field effect transistors

The formation of self-aligned Ti(Si_(1−x)Ge_(x))₂ on submicron lines is described. The silicide/germanide is formed by reacting sputtered Ti with epitaxially grown Si_(1−x)Ge_(x) of composition and thickness relevant to high mobility Si_(1−x)Ge_(x) channel field effect transistors. Ti(Si_(1−x)Ge_(x))₂ formation on narrow lines was carried out on phosphorous doped material, because of the well known difficulties of forming silicide on heavily n-doped silicon. A companion set of boron doped blanket films was also processed. The results show that the process temperature required for the minimization of silicide/germanide sheet resistance is reduced as compared to silicide formation on Si alone. However, the silicide/germanide films agglomerate with increased high temperature processing more easily than pure silicide. The thermal stability is degraded more for films with higher Ge content and is a strong function of dopant type. Silicide/germanide formation on phosphorous doped Si_(1−x)Ge_(x) layers with x = 10% have a line width dependence similar to silicide formation. Formation on phosphorous doped Si_(1−x)Ge_(x) layers with x = 27% display an inverse line width dependence, with higher overall sheet resistance. Formation of silicide/germanide on blanket films of boron doped Si_(1−x)Ge_(x) with x = 27% behaved similar to the formation of silicide on silicon.     

A low thermal budget self-aligned Ti silicide technology usinggermanium implantation for thin-film SOI MOSFET's

In this paper, a titanium salicide technology with a very low thermal annealing temperature using germanium implantation for thin film SOI MOSFET's is investigated in detail. Ti silicide formation on the amorphous silicon generated by germanium implantation is studied. Compared to the conventional Ti salicide process, the Ti silicidation temperature is significantly lowered and the silicide depth is well controlled through the pre-amorphized layer. Therefore, the potential problems of the salicide process for SOI MOSFET's such as lateral voids, dopant segregation, thermal agglomeration, and increase of resistance on narrow gate are suppressed by germanium implantation. With the Ge pre-amorphization salicide process, a very low silicide contact resistance is obtained and sub-0.25-μm SOI MOSFET's are fabricated with good device characteristics     

U型凹槽电极硅MSM结构光电探测器的研制

为了提高硅MSM结构光电探测器的光电响应度,制备了U型凹槽电极结构的探测器.5 V偏压下,对650 nm波长入射光的绝对光电响应度测试表明,凹槽电极结构的探测器最大光电响应度值为0.486 A/W,比同样尺寸的平版结构光电探测器提高了约6倍.文中也对比了具有抗反射膜和不具有抗反射膜的器件相对响应光谱的差别,并且比较分析了叉指间隙分别为5 μm和10 μm器件光电响应的不同.     

Scaling Effects on the Electrochemical Performance of poly(3,4‐ethylenedioxythiophene (PEDOT), Au,and Pt for Electrocorticography Recording

Reduced contact size would permit higher resolution cortical recordings, but the effects of diameter on crucial recording and stimulation properties are poorly understood. Here, the first systematic study of scaling effects on the electrochemical properties of metallic Pt and Au and organic poly(3,4‐ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS) electrodes is presented. PEDOT:PSS exhibits better faradaic charge transfer and capacitive charge coupling than metal electrodes, and these characteristics lead to improved electrochemical performance and reduced noise at smaller electrode diameters. PEDOT:PSS coating reduces the impedances of metallic electrodes by up to 18x for diameters <200 µm, but has no effect for millimeter scale contacts due to the dominance of series resistances. Therefore, the performance gains are especially significant at smaller diameters and lower frequencies essential for recording cognitive and pathological activities. Additionally, the overall reduced noise of the PEDOT:PSS electrodes enables a lower noise floor for recording action potentials. These results permit quantitative optimization of contact material and diameter for different electrocorticography applications.     

A Bondable Metallization Stack That Prevents Diffusion of Oxygen and Gold into Monolithically Integrated Circuits Operating Above 500°C

We investigate use of tantalum silicide (TaSi₂, 400 nm)/platinum (Pt, 200 nm)/iridium (Ir, 200 nm)/platinum (Pt, 200 nm) as both a bond metal and a diffusion barrier to prevent oxygen (from air) and gold (from the wire bond) from infiltrating silicon carbide (SiC) monolithically integrated circuits operating above 500°C for over 1000 h in air. The TaSi₂/Pt/Ir/Pt metallization is easily bonded for electrical connection to off-chip circuitry and does not require extra anneals or masking steps. It can be used directly on ohmic contact metals, dielectric insulating layers, or interconnect metal, because it adheres to silicon dioxide (SiO₂), silicon nitride (Si₃N₄), and titanium (Ti). In this study, we investigate use of the new metallization of TaSi₂/Pt/Ir/Pt (in deposition order) with TaSi₂ resting on top of a Ti-SiC contact annealed at 600°C for 30 min in nitrogen, which allows the TaSi₂ layer to react with the bottom platinum layer to form the Pt₂Si diffusion barrier at the Pt-Ir interface. Since the iridium layer does not readily form a silicide, it prevents the silicon from migrating into the topmost platinum layer during further annealing or high-temperature integrated circuit operation. This leaves a pure platinum layer at the surface, ideal for gold wire bonding. We discuss the characteristics of the TaSi₂/Pt/Ir/Pt metallization at 500°C after 10 h, 100 h, and 1000 h in air ambient and N₂ ambient. Auger electron spectroscopy (AES) depth profiles of the metallization and field-emission scanning electron microscopy-focused ion beam (FESEM-FIB) cross-sections are also discussed.     

TiSi2的形成及其在浅结多晶硅发射极工艺中的应用

采用蒸发淀积、快速热退火等技术，通过Ｔｉ／Ｓｉ，Ｔｉ多晶硅固相反应，形成高电导均匀的ＴｉＳｉ２薄膜，并将这种钛硅化物形成技术应用于浅结多晶硅发射极工艺中，自对准形成钛硅化物薄膜，以形成良好的欧姆接触减小器件互连线电阻。本文介绍了钛与单晶硅、多晶硅形成的硅化物及其在浅结多晶硅发射极工艺中的应用研究。     

Sem,auger spectroscopy and ion backscattering techniques applied to analyses of Au/refractory metallizations

The concurrent application of the SEM, AES, X-ray diffractometry and Rutherford Backscattering (RBS) techniques to Au/refractory metallizations is analyzed with respect to the study of thin film interdiffusion, intermetallic formation, microcracking and oxidation phenomena. The SEM in the backscatter electron image mode was used for resolution of intermetallic compounds and interdiffusion products, while AES and RBS analyses were used to obtain depth-composition profiles. The metallizations studied were Ta/Pt/Ta/Au and W/Au. The combination of Ta/Pt/Ta and Ti/Pt have been shown to be effective barriers to gold-silicon interdiffusion. Defects in the tungsten barrier were found to result in silicon migration to the front surface and gold migration toward the substrate at temperatures between 550°C-700°C . The diffusion constants for Au-Ta and Au-Pt interdiffusion have been determined from the AES data.     

A novel elevated MOSFET source/drain structure

A vertically layered elevated drain structure is proposed which is suitable, in terms of reliability and performance for MOSFET scaling down to the 0.25-μm level without a reduction of the supply voltage below 3.3 V. In this structure, a low-doped polysilicon or crystalline silicon spacer (layer) is used to solve the hot-carrier problem. In contrast to existing device structures, which try to minimize the impact ionization rate, this structure rests on the idea that high-impact ionization and even high hot-carrier injection (HCl) rates can be tolerated as long as they are not detrimental to the device characteristics     

The effect of biased spacers on LDD MOSFET behavior

The concept of using LDD spacers that are independently biased with respect to the gate electrode is presented. It is shown that the lateral electric field is strongly influenced by the drain polysilicon spacer potential. Depending on the N^- dose, the peak substrate currents can be either enhanced or reduced by shorting the drain polysilicon spacer to the drain potential. Short-channel LDD MOSFETs have been fabricated with polysilicon LDD spacers shorted to the source and drain electrodes by titanium silicide     

Limitation of spacer thickness in titanium salicide ULSI CMOStechnology

The isolation integrity of various gate-spacer thicknesses in 15-20-μm-wide MOS devices with and without titanium salicide is discussed. The gate-spacer thickness varies from 25 to 100 nm. Experimental results show that for Ti salicided devices with only a 25-nm-thick gate spacer, a broad spectrum of gate-drain (source) breakdown voltages, at a leakage current level of 2 μA, is measured in the range of 1.5 to 10 V. Using a specific gate-spacer tester with a total gate-spacer perimeter near 10 cm in length, the statistical data taken over 100 tested chips show that as the thickness of the gate spacer is reduced to less than 50 nm, the gate leakage increases to 10 ^-9 A under a gate bias equal to 5 V. The leakage of the thin gate spacer is attributed to the formation of Ti-rich oxide during the Ti self-aligned silicide process, which degrades the isolation integrity and generates a leakage path. The implications of this leakage mechanism for ULSI technologies are discussed     

Test structure to investigate the series resistance components ofsource/drain structure

The source and drain (S/D) structure is a key element in scaling down the MOSFET for low-power applications below 0.25-μm dimensions. Here, we report on a simple test structure and show how more detailed information on the parasitic series resistance components of deep submicron devices can be obtained. Specifically, the dependence of the different resistance components on the process parameters like dose and energy of implantation, temperature treatment, spacer width, and silicide formation can be investigated with high accuracy     

Ni- and Co-based silicides for advanced CMOS applications

The scaling behavior of Co, Co–Ni and Ni silicides to sub-40 nm gate length CMOS technologies with sub-100 nm junction depths was evaluated. Limitations were found for Co and Co–Ni alloy silicides, which exhibited an increase in sheet resistance at gate lengths below 40 nm and required high processing temperatures to achieve low junction leakage. Ni silicide was shown, in contrast, to have good scaling behavior, with a decrease in sheet resistance for decreasing gate lengths down to 30 nm, lower diode leakage (at similar sheet resistance) and lower silicide to p+ Si contact resistance than Co silicide. Key material issues impacting the applicability of NiSi to CMOS technologies were investigated. Studies of the kinetics of Ni₂Si growth were used to design a process that avoids excessive silicidation of small features. The thermal degradation mechanisms of NiSi films were also studied. Thin films degraded morphologically with activation energies of 2.4 eV. Thick films degraded morphologically at low temperatures and by transformation to NiSi₂ at high temperatures, suggesting a higher activation energy for the latter mechanism. Pt alloying was shown to help stabilize NiSi films against morphological degradation.