TFT-LCD驱动芯片内置SRAM的低功耗设计

内置SRAM是单片集成TFT-LCD驱动控制芯片中的图像数据存储模块.针对内置SRAM的低功耗设计要求,采用HWD结构和动态逻辑的字线译码电路,实现了1.8Mb SRAM的低功耗设计.电路采用0.18μm CMOS工艺实现,Hspice和Ultrasim仿真结果表明,与静态字线译码电路相比,功耗减小了20%;与DWL结构相比,功耗减小了16%;当访存时钟频率为31MHz时,SRAM存储单元的读写时间小于8ns,电源峰值功耗小于123mW,静态功耗为0.81mW.     

低功耗绝热SRAM

文章提出了一种新的绝热电路,并以该绝热电路为驱动,设计了一种低功耗绝热SRAM.由于所提出的绝热电路能以完全绝热的方式回收位线和字线上大开关电容的电荷,因此使该SRAM的功耗大大减小.我们采用0.25μm TSMC工艺,在时钟频率25～200MHz范围内对绝热SRAM进行了能耗和功能的HSPICE仿真,结果显示,与用传统的CMOS电路设计的SRAM相比,可节能80%左右.     

三值钟控绝热静态随机存储器设计

通过对多值逻辑、绝热电路和三值SRAM结构的研究,提出一种新颖的三值钟控绝热静态随机存储器(SRAM)的设计方案。该方案利用NMOS管的自举效应,以绝热方式对SRAM的行列地址译码器、存储单元、敏感放大器等进行充放电,有效恢复储存在字线、位线、行列地址译码器等大开关电容上的电荷,实现三值信号的读出写入和能量回收。PSPICE模拟结果表明,所设计的三值钟控绝热SRAM具有正确的逻辑功能和低功耗特性,在相同的参数和输入信号情况下,与三值常规SRAM相比,节约功耗达68%。     

三电平字线的4sns 256k CMOSSRAM

由于电路和工艺技术的不断进步,MOSRAM的密度仍在增加。特别是已经采用了几种新的电路技术,它们使高密度SRAM有低的速度功耗乘积。下面讨论的 32k×8位静态RAM包括一个与三电平字线相结合的地址渡越激活电路,它在1MHz时产生7mW的激活功率和40mA的峰值电流。获得了45ns的地址存取时间。     

CMOS/SOI 64Kb静态随机存储器

对一种CMOS/SOI 64Kb静态随机存储器进行了研究,其电路采用8K×8的并行结构体系．为了提高电路的速度,采用地址转换监控(Address-Translate-Detector,ATD)、两级字线(Double-Word-Line,DWL)和新型的两级灵敏放大等技术,电路存取时间仅40ns;同时,重点研究了SOI静电泄放(Electrostatic-Discharge,ESD)保护电路和一种改进的灵敏放大器,设计出一套全新ESD电路,其抗静电能力高达4200—4500V．SOI 64Kb CMOS静态存储器采用1.2μm SOI CMOS抗辐照工艺技术,芯片尺寸为7.8mm×7.24mm．     

CMOS/SOI64Kb静态随机存储器

对一种 CMOS/ SOI6 4Kb静态随机存储器进行了研究 ,其电路采用 8K× 8的并行结构体系 .为了提高电路的速度 ,采用地址转换监控 ( Address- Translate- Detector,ATD)、两级字线 ( Double- Word- L ine,DWL)和新型的两级灵敏放大等技术 ,电路存取时间仅 40 ns;同时 ,重点研究了 SOI静电泄放 ( Electrostatic- Discharge,ESD)保护电路和一种改进的灵敏放大器 ,设计出一套全新 ESD电路 ,其抗静电能力高达 42 0 0— 45 0 0 V.SOI6 4KbCMOS静态存储器采用 1.2 μm SOI CMOS抗辐照工艺技术 ,芯片尺寸为 7.8m m× 7.2 4mm     

亚65nm静态随机存储器稳定性提高技术

CMOS工艺进入到65nm节点后,工作电压降低,随机掺杂导致阈值电压变化增大,给SRAM的读写稳定性带来挑战。介绍了目前业界最新的主要稳定性提高技术。双电源电压、直流分压、电荷共享和电容耦合通过改变字线或者存储单元电压来提高读写稳定性,这些技术都采用外加读写辅助电路来实现;超6管存储单元通过在传统6管单元上增加晶体管,有效提高了读写稳定性;三维器件FinFET构成的SRAM具有传统器件无法比拟的高速、高稳定性、面积小的特点。对这些技术的优缺点作了分析比较。     

256KbCMOS模拟SRAM

日本东芝公司最近研制成功存取时间为25ns的256Kb模拟SRAM.这种型号为TC51832P-85的产品系列包括由一个晶体管和一个电容器组成的存储单元(与DRAM相同)和CMOS结构的外部电路(32K×8位).字线采用聚硅和聚铝的双层结构.字线的     

基于补偿电路的SRAM读操作跟踪电路设计

在传统静态随机存储器（SRAM）读操作跟踪电路中,生产工艺和温度的偏差会直接影响到对SRAM中存储数据的正确读取。因此,在本文中,我们采用工艺拐点补偿和温度补偿的方法,设计出了新型SRAM读操作跟踪电路。所设计跟踪电路,通过在不同工艺拐点和不同温度的情况下,对时序追踪字线DBL补偿不同大小的电流,从而减小灵敏放大器输入位线电压差对工艺拐点和温度的敏感度。有效减小了工艺拐点和温度对于SRAM读操作的影响,提高了SRAM的良率。基于SMIC 40nm CMOS工艺,对上述读操作跟踪电路进行了仿真,并且分别对补偿前后进行了10000次蒙特卡罗仿真与比较,仿真结果验证了所设计电路的可靠性和有效性。     

一款异步256kB SRAM的设计

在集成电路设计制造水平不断提高的今天,SRAM存储器不断朝着大容量、高速度、低功耗的方向发展。文章提出了一款异步256kB(256k×1)SRAM的设计,该存储器采用了六管CMOS存储单元、锁存器型灵敏放大器、ATD电路,采用0.5μm体硅CMOS工艺,数据存取时间为12ns。     

An 8 ns 4 Mb serial access memory

A new architecture for serial access memory is described that enables a static random access memory (SRAM) to operate in a serial access mode. The design target is to access all memory address serially from any starting address with an access time of less than 10 ns. This can be done by all initializing procedure and three new circuit techniques. The initializing procedure is introduced to start the serial operation at an arbitrary memory address. Three circuit techniques eliminate extra delay time caused by an internal addressing of column lines, sense amplifiers, word lines, and memory cell blocks. This architecture was successfully implemented in a 4-Mb CMOS SRAM using a 0.6 μm CMOS process technology. The measured serial access time was 8 ns at a single power supply voltage of 3.3 V     

A 3.3-V 12-ns 16-Mb CMOS SRAM

A 16-Mb CMOS SRAM having an access time of 12 ns under a 3.3-V supply has been developed with a 0.4-μm process technology. An address access time of 12 ns has been achieved by an optimized architecture, the use of an automated transistor size optimizer, and a read-bus midlevel preset scheme (RBMIPS). For better yield and efficient testing, an on-chip test circuit with three test modes has been implemented     

A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperature

A GaAs 1 K×4-kb SRAM designed using a novel circuit technology is described. To reduce the temperature dependence and the scattering of the access time, it was necessary to increase the signal voltage swing and to reduce the leakage current in access transistors of unselected memory cells. In the 4-kb SRAM, source-follower circuits were adopted to increase the voltage swing, and the storage nodes of unselected memory cells were raised by about 0.6 V to reduce the subthreshold leakage current in the access transistors. The 4-kb SRAM was fabricated using 1.0-μm self-aligned MESFETs with buried p-layers beneath the FET regions. A maximum address access time of 7 ns and a power dissipation of 850 mW were obtained for the galloping test pattern at 75°C. Little change in the address access time was observed between 0 and 75°C     

用SOI技术提高CMOS SRAM的抗单粒子翻转能力

提高静态随机存储器（SRAM）的抗单粒子能力是当前电子元器件抗辐射加固领域的研究重点之一。体硅CMOS SRAM不作电路设计加固则难以达到较好抗单粒子能力,作电路设计加固则要在芯片面积和功耗方面做出很大牺牲。为了研究绝缘体上硅（SOI）基SRAM芯片的抗单粒子翻转能力,突破了SOI CMOS加固工艺和128kb SRAM电路设计等关键技术,研制成功国产128kb SOI SRAM芯片。对电路样品的抗单粒子摸底实验表明,其抗单粒子翻转线性传输能量阈值大于61．8MeV／（mg／cm^2）,优于未做加固设计的体硅CMOS SRAM。结论表明,基于SOI技术,仅需进行器件结构和存储单元的适当考虑,即可达到较好的抗单粒子翻转能力。     

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layoutsense amplifiers

A 16-Mb CMOS SRAM using 0.4-μm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm² is fabricated and an address access time of 12.5 ns has been achieved     

A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits

The dual-sensing-latch circuit proposed here can solve the synchronization problem of the conventional wave-pipelined SRAM and the proposed source-biased self-resetting circuit reduces both the cycle and access time of cache SRAM's. A 16-kb SRAM using these circuit techniques was designed, and was fabricated with 0.25-μm CMOS technology. Simulation results indicate that this SRAM has a typical clock access time of 2.6 ns at 2.5-V supply voltage and a worst minimum cycle time of 2.6 ns     

Automated bias control (ABC) circuit for high-performance VLSIs

A biasing scheme for sensing circuits, namely an automated bias control (ABC) circuit, for high-performance VLSIs is described. The ABC circuit can automatically gear the output level of sensing circuits to the input threshold voltage of the succeeding CMOS converters. The sensing performance can be accelerated with the ABC circuit either by reducing the excessive signal level margin between the sensing circuits and the CMOS converters or by reducing extra stages of signal amplification. Since feedback control of the ABC circuit ensures correct DC biasing even under large process deviations and circuit condition changes, a wider operation margin can also be obtained. Three successful applications of the ABC circuit are reported: a sense amplifier, an address transition detector (ATD), and an ECL-CMOS input buffer. A 64-kb BiCMOS SRAM employing the proposed sense amplifier and the ATD has been fabricated with a 0.8-μm 9-GHz BiCMOS technology. The SRAM has an address access time of 4.5 ns     

A 9-ns 1-Mbit CMOS SRAM

A 1-Mbit CMOS static RAM (SRAM) with a typical address access time of 9 ns has been developed. A high-speed sense amplifier circuit, consisting of a three-stage PMOS cross-coupled sense amplifier with a CMOS preamplifier, is the key to the fast access time. A parallel-word-access redundancy architecture, which causes no access time penalty, was also incorporated. A polysilicon PMOS load memory cell, which had a large on-current-to-off-current ratio, gave a much lower soft-error rate than a conventional high-resistance polysilicon load cell. The 1-Mbit SRAM, fabricated using a half-micrometer, triple-poly, and double-metal CMOS technology, operated at a single supply voltage of 5 V. An on-chip power supply converter was incorporated in the SRAM to supply a partial internal supply voltage of 4 V to the high-performance half-micrometer MOS transistors.<>     

一种基于全数字锁相环的SRAM实速测试方案

提出了一种采用实速测试方式测试SRAM性能参数及可靠性的方案。该方案在内建自测试(BIST)电路的基础上,通过增加一个超高速ADPLL为SRAM性能的实速测试提供一个高频时钟,同时还加入延时链来产生不同相位的4个时钟。通过调整这4个时钟的相位来获得SRAM的关键性能参数,如存取时间、地址建立和保持时间等。该方案在UMC 55nm CMOS标准逻辑工艺下流片验证。测试结果显示,SRAM最大测试工作频率约为1.3GHz,测试精度为35ps。     

An experimental 1-Mbit cache DRAM with ECC

A cache DRAM which consists of a dynamic RAM (DRAM) as main memory and a static RAM (SRAM) as cache memory is proposed. An error checking and correcting (ECC) scheme utilizing the wide internal data bus is also proposed. It is constructed to be suitable for a four-way set associated cache scheme with more than a 90% hit rate estimated to be obtained. An experimental cache DRAM with 1-Mb DRAM and 8-kb SRAM has been fabricated using a 1.2-μm, triple-polysilicon, single-metal CMOS process. A SRAM access time of 12 ns and a DRAM access time of 80 ns, including an ECC time of 12 ns, have been obtained. Accordingly, an average access time of 20 ns is expected under the condition that the hit rate is 90%. The cache DRAM has a high-speed data mapping capability and high reliability suitable for low-end workstations and personal computers