Model to predict gate tunneling current of plasma oxynitrides

Two key parameters for silicon MOSFET scaling, equivalent oxide thickness (EOT) and gate leakage current density (J/sub g/) are measured and modeled for silicon oxynitride (Si-O-N) gate dielectrics formed by plasma nitridation of SiO/sub 2/. It is found that n-MOSFET inversion J/sub g/ is larger than p-MOSFET inversion J/sub g/ when the gate dielectric consists of less than 27% nitrogen atoms, indicating substrate injection of electrons is dominant for this range of plasma nitrided Si-O-N. To examine the intrinsic scaling of Si-O-N, we model EOT and n-MOSFET J/sub g/ for sub-2-nm physically thick gate dielectrics as a function of film physical thickness and nitrogen content. The model has four free fitting parameters and unlike existing models does not assume a priori the values of the oxide and nitride dielectric constant, barrier height, or effective mass. It indicates that at a given EOT, leakage current of n-MOSFETs with Si-O-N gate dielectrics reaches a minimum at a specific nitrogen content. Through the use of this model, we find that plasma nitrided Si-O-N can meet the 65-nm International Technology Roadmap for Semiconductors specifications for J/sub g/, and we estimate the nitrogen concentration required for each node and application.     

Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide

The degradation induced by substrate hot electron (SHE) injection in 0.13-/spl mu/m nMOSFETs with ultrathin (/spl sim/2.0 nm) plasma nitrided gate dielectric was studied. Compared to the conventional thermal oxide, the ultrathin nitrided gate dielectric is found to be more vulnerable to SHE stress, resulting in enhanced threshold voltage (V/sub t/) shift and transconductance (G/sub m/) reduction. The severity of the enhanced degradation increases with increasing nitrogen content in gate dielectric with prolonged nitridation time. While the SHE-induced degradation is found to be strongly related to the injected electron energy for both conventional oxide , and plasma-nitrided oxide, dramatic degradation in threshold voltage shift for nitrided oxide is found to occur at a lower substrate bias magnitude (/spl sim/-1 V), compared to thermal oxide (/spl sim/-1.5 V). This enhanced degradation by negative substrate bias in nMOSFETs with plasma-nitrided gate dielectric is attributed to a higher concentration of paramagnetic electron trap precursors introduced during plasma nitridation.     

The performance and reliability of PMOSFET's with ultrathin siliconnitride/oxide stacked gate dielectrics with nitrided Si-SiO2interfaces prepared by remote plasma enhanced CVD and post-depositionrapid thermal annealing

Ultrathin (~1.9 nm) nitride/oxide (N/O) dual layer gate dielectrics have been prepared by the remote plasma enhanced chemical vapor deposition (RPECVD) of Si₃N₄ onto oxides. Compared to PMOSFET's with heavily doped p⁺-poly-Si gates and oxide dielectrics, devices incorporating the RPECVD stacked nitrides display reduced tunneling current, effectively no boron penetration and improved interface characteristics. By preventing boron penetration into the bulk oxide and channel region, gate dielectric reliability and short channel effects are significantly improved. The hole mobility in devices with N/O dielectrics with equivalent oxide thickness between 1.8 nm and 3.0 nm is not significantly degraded. Because nitrogen is transported to the substrate/dielectric interface during post-deposition annealing, degradation of mobility during hot carrier stressing is significantly reduced for N/O devices. Compared with oxide, the tunneling current for N/O films with ~1.9 nm equivalent oxide thickness is lower by about an order of magnitude due to the larger physical thickness. Suppression of boron transport in nitride layers is explained by a percolation model in which boron transport is blocked in sufficiently thick nitrides, and is proportional to the oxide fraction in oxynitride alloys     

A metal-gate self-aligned MOSFET using nitride oxide

A new method for making metal-gate self-aligned transistors using a thin nitrided oxide (12 nm) as a gate dielectric has been demonstrated. The nitrided thermal oxide acts as both a local oxidation mask and the final gate dielectric to produce a self-aligned thick oxide in the source-drain region. The thick oxide reduces the overlap capacitance down to that of a self-aligned polysilicon-gate device while allowing the use of a metal gate with a much lower resistivity than the more commonly used polycrystalline silicon. A high-frequency capacitance-voltage technique has been used to measure gate to source-drain overlap capacitance. The overlap capacitance was measured for a range of source-drain oxide thicknesses from 370 down to 255 nm. The capacitance increased from 0.64 to 0.74 fF/µm. The overlap capacitance of a self-aligned polycrystalline silicon-gate device with similar processing parameters was 0.98 fF/µm. The channel mobility has been determined to be approximately 350 cm²/V . s. Transistors with channel lengths as low as 0.7/µm were fabricated. Ring oscillators were also fabricated with stage-delays as low as 300 ps at 1.5 V and power-delay products of 70 fJ.     

HfTiO氮化退火对MOS器件电特性的影响

采用磁控溅射方法,在Si衬底上淀积HfTiO高k介质,研究了NO、N2O、NH3和N2不同气体退火对MOS电特性的影响。结果表明,由于NO氮化退火能形成类SiO2/Si界面特性的HfTiSiON层,所制备的MOS器件表现出优良的电特性,即低的界面态密度、低的栅极漏电和高的可靠性。根据MOS器件栅介质(HfTiON/HfTiSiON)物理厚度变化(ΔTox)和电容等效厚度变化(ΔCET)与介质(HfTiON)介电常数的关系,求出在NO气氛中进行淀积后退火处理的HfTiON的介电常数达到28。     

Understanding the effects of wave function penetration on theinversion layer capacitance of NMOSFETs

A comprehensive analysis of the effects of wave function penetration on the capacitance of NMOS capacitors has been performed for the first time, using a self-consistent Schrodinger-Poisson solver. The study reveals that accounting for wave function penetration into the gate dielectric causes carrier profile to be shifted closer to the gate dielectric reducing the electrical oxide thickness. This shift increases with increasing gate voltage. For example, in one simulation, the peak is shifted by about 0.2 nm at a surface field of 1.96 MV/cm and 0.33 nm at a surface field of 3.7 MV/cm. This shifting results in all increased capacitance. The increase in capacitance observed in the inversion region is relatively insignificant when a poly gate electrode with a doping of less than 1×10²⁰ cm^-3 is used due to the poly-depletion effect. A physical picture of the effect of physical thickness on the tunneling current is also presented     

Characteristics of thermally nitrided silicon dioxide film and plasma enhancement

After reviewing characteristics of thermally nitrided silicon dioxide films, plasma enhanced nitridation is described. The plasma technique makes possible reduction of the nitridation temperature by activating reaction species. Silicon dioxide films of about 10 nm thickness were nitrided in ammonia gas plasma, for example, at 1000‡C and at a pressure of 40 Pa. From the results of the AES depth profiles and the N_ss distribution, good dielectric and interfacial properties have been obtained via plasma nitridation. The plasma nitroxide films are useful for gate insulators of small MOSFETs in future VLSI.     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

0.86-nm CET Gate Stacks With Epitaxial$hboxGd_2hboxO_3$High-$k$Dielectrics and FUSI NiSi Metal Electrodes

In this letter, ultrathin gadolinium oxide$(hboxGd_2hboxO_3)$high-$k$gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a$hboxGd_2hboxO_3$thickness of 3.1 nm yield a capacitance equivalent oxide thickness of$ CET = hbox0.86 hboxnm$. The extracted dielectric constant is$k = hbox13-hbox14$. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond.     

Temperature effect on gate leakage currents in gate dielectric films of GaAs MOSFET

The gate dielectrics of Ga₂O₃(As₂O₃) of the GaAs MOSFET were prepared by a low-cost and low-temperature liquid-phase chemically enhanced oxidation method. The temperature and oxide thickness dependence of gate dielectric films on GaAs MOSFET have been investigated. The leakage current and dielectric breakdown field were both studied. Both gate leakage current density and breakdown electrical field were found to depend on the oxide thickness and operating temperature. The increasing trend in gate leakage current and the decreasing trend in breakdown electrical field were observed upon reducing oxide thickness from 30 to 12 nm and increasing operating temperature from −50°C to 200°C.     

Electrical and Reliability Characteristics of 12- Å Oxynitride Gate Dielectrics by Different Processing Treatments

Various ultrathin oxynitride gate dielectrics of similar thickness (~1.2 nm) fabricated by a combination of an in situ steam generated and remote plasma nitridation treatment (RPN), an RPN with rapid thermal NO annealing (RPN-NO), and an RPN with rapid thermal O₂ annealing (RPN-O₂) are reported in this paper. The RPN-NO gate dielectric films show superior interface properties including relatively high nitrogen concentration near the poly-Si/oxide interface and smooth interfaces, excellent electrical characteristics in terms of lower leakage current, better electron and hole channel mobility, higher drive current, and significantly improved reliability such as stress-induced leakage current, hot carrier injection, and negative bias temperature instability, compared to other gate dielectrics fabricated by different processes.     

Rapid thermal nitridation of thin SiO2 films

An alternative to SiO₂ for gate dielectric applications in MIS devices is nitrided silicon dioxide. A study of this material is presented in this paper. Thin SiO₂ layers (10 nm minimum thickness) were grown on silicon substrates and subsequently nitrided in ammonia at 1 atm using a rapid thermal processing system. Nitridation times ranged from 3 sec to 60 sec at temperatures from 900 to 1200‡ C. The resulting films were then characterized using a variety of techniques including high resolution TEM, XPS, AES, SIMS, and electrical measurements (C-V). Higher temperatures and longer processing times resulted in the accumulation of nitrogen at the film surface and at the Si/SiO₂ interface. As expected, the electrical characteristics of the nitrided films were strongly influenced by the processing conditions. The morphology of the interface, as revealed by high-resolution TEM, was also altered by the nitridation process, especially for high processing temperatures (>1000° C).     

Physical models for predicting plasma nitrided Si-O-N gate dielectric properties from physical metrology

Using simple physical models, specific relationships between parameters measured by X-ray photoelectron spectroscopy (XPS) and those measured on MOS transistors are described for silicon oxynitride gate dielectrics prepared by plasma nitridation. Correlations are established between the equivalent oxide thickness (EOT) and gate leakage current and the nitrogen anneal dose and physical thickness as measured by XPS. These correlations, from devices in the 10 to 13 /spl Aring/ EOT range, allow accurate estimates of electrical thickness and leakage without device fabrication, enabling both development and process monitoring for sub-130-nm node gate dielectrics.     

Effects of radiation and charge trapping on the reliability of high-κ gate dielectrics

The radiation response and long term reliability of alternative gate dielectrics will play a critical role in determining the viability of these materials for use in future space applications. The total dose radiation responses of several near and long term alternative gate dielectrics to SiO₂ are discussed. Radiation results are presented for nitrided oxides, which show no change in interface trap density with dose and oxide trapped charge densities comparable to ultra thin thermal oxides. For aluminum oxide and hafnium oxide gate dielectric stacks, the density of oxide trapped charge is shown to depend strongly on the film thickness and processing conditions. The alternative gate dielectrics discussed here are shown to have effective trapping efficiencies that are up to 15 to 20 times larger than thermal SiO₂ of equivalent electrical thickness. A discussion of single event effects in devices and ICs is also provided. It is shown that some alternative gate dielectrics exhibit excellent tolerance to heavy ion induced gate dielectric breakdown. However, it is not yet known how irradiation with energetic particles will affect the long term reliability of MOS devices with high-κ gate dielectrics in a space environment.     

Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

Reduction in static-power dissipation (gate leakage) by using nitrided oxides comes at the expense of enhanced negative-bias temperature instability (NBTI). Therefore, determining the nitrogen content in gate oxides that can simultaneously optimize gate-leakage and NBTI degradation is a problem of significant technological relevance. In this paper, we experimentally and theoretically analyze wide range of gate-leakage and NBTI stress data from a variety of plasma-oxynitride gate dielectric devices to establish an optimization scheme for gate-leakage and NBTI degradation. Calculating electric fields and leakage current both numerically and using simple analytical expressions, we demonstrate a design diagram for arbitrary nitrogen concentration and effective oxide thickness that may be used for process and IC design.     

Effects of nitric oxide annealing of thermally grown silicondioxide characteristics

The effects of nitric oxide (NO) annealing on conventional thermal oxides are reported in this letter. The oxide thickness increase, resulting from NO annealing, is found to be only a few angstroms (<0.5 nm) and independent on the initial oxide thickness. Furthermore, both the electrical and physical characteristics are improved. This technique is expected to achieve sub-5 nm high quality ultrathin dielectric films for the applications in EEPROM's and ULSI     

Characteristics of the NO dielectric film with low pressure chemical vapor deposition in-situ nitridation

We investigated the formation of the thin NO dielectric films by in-situ nitridation of native oxide, and subsequent deposition of silicon nitride in the low pressure chemical vapor deposition systems for the application to the capacitors in high density dynamic random access memory. The native oxide was nitrided at elevated temperatures of 690 or 780°C in the flowing ammonia gas atmosphere, and nitride was deposited by flowing silane gas additionally immediately after the nitridation process. By in-situ nitridation process, we could obtaine 5 and 4.5 nm thick (equivalent oxide thickness) nitride/oxide (NO) dielectric films. These films were characterized to be electrically more reliable than the conventional oxide/nitride/oxide (ONO) films of the same equivalent oxide thickness. The nitrided NO films also showed lower leakage current and higher breakdown voltage than conventional ONO films. We obtained electrically most reliable NO films by loading the wafer at 400°C and nitriding the native oxide at 780°C.     

1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O)composites prepared by RPECVD/oxidation process

Ultrathin nitride/oxide (~1.5/0.7 nm) dual layer gate dielectrics have been formed using remote plasma enhanced CVD of nitride onto plasma-grown oxide interface layers. High accumulation capacitance (1.72 μF/cm²) is measured and the equivalent oxide thickness is 1.6 nm after quantum effect corrections. Compared to 1.6 nm oxides, a tunneling current reduction of more than 100 fold is found for devices with 1.6 nm N/O dielectrics due to increased film thickness and interface nitridation. Hole channel mobility decreases by about 5%, yielding very good P-MOSFET current drive. Excellent dielectric reliability and interface robustness are also demonstrated for P-MOSFET's with N/O dielectrics     

Thermally-enhanced remote plasma nitrided ultrathin (1.65 nm) gateoxide with excellent performances in reduction of leakage current andboron diffusion

Ultrathin thermally enhanced remote plasma nitrided oxides (TE-RPNO) with equivalent oxide thickness down to 1.65 nm are fabricated to investigate their leakage current reduction and boron diffusion barrier performances. A PMOSFET with TE-RPNO, compared to its conventional oxide counter-part, yields almost one order magnitude lower gate leakage current, less flatband voltage changes in high boron implantation dose or activation temperature, and shows broader process windows in the tradeoff between boron penetration and dopant activation     

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.