Cubic paraelectric (nonferroelectric) perovskite PLT thin filmswith high permittivity for ULSI DRAMs and decoupling capacitors

Polycrystalline paraelectric perovskite thin films in the Pb-La-Ti-O or PLT (28 mol.% La) system have been studied. Thin (0.5-μm) films were integrated onto 3-in Pt/Ti/SiO₂/(100) Si wafers by the sol-gel processing technique. Low-field dielectric measurements yielded dielectric permittivity and loss tangent of 1400 and 0.015, respectively, while high-field Sawyer-Tower measurements (P-E) showed linear behavior up to 40 kV/cm, which approached saturation at 200 kV/cm. Pulse charging transient and current-voltage measurements indicated a high charge storage density (15.8 μC/cm²) and low leakage current density (0.50 μA/cm²) under a field of 200 kV/cm. The charging time for a 1-μm² PLT capacitor at 200 kV/cm was estimated to be 0.1 ns. The preliminary data demonstrate that paraelectric PLT thin films have excellent potential for use in ULSI DRAMs and as decoupling capacitors     

Electrical characteristics of oxide-nitride-oxide films formed ontunnel-structured stacked capacitors

Current conduction mechanism of oxide-nitride-oxide films formed on tunnel-structured stacked capacitor (TSSC) was studied. At positive and negative bias, the Poole-Frenkel (P-F) conduction of holes in the nitride (SiN_x) film dominates the total leakage current. From the P-F plot, the relative dielectric constant of the SiN_x was calculated. The electric field inside the structure was also calculated by assuming the model that characterizes the electrode shape inside the tunnel. From the results, the reason why the reliability of the TSSC is not lowered in comparison with the conventional stacked capacitor is discussed     

Properties of thin oxide-nitride-oxide stacked films

Electronic conduction, charge trapping and dielectric breakdown were studied on thin stacked layers of SiO₂-Si₃N₄-SiO₂ with Al or poly-Si gate on Si. Conductivity and breakdown strength are roughly the same as observed on single SiO₂ films but the average dielectric constant is higher than that for SiO₂. Stacks with plasma CVD SiO₂ layers show somewhat poorer breakdown strengths than those with thermally grown SiO₂ films. The charging behavior of the stacks is more pronounced than that of single films. Moreover, they break down at a lower total injected charge.     

Investigation of PECVD dielectrics for nondispersivemetal-insulator-metal capacitors

Metal-insulator-metal (MIM) capacitors with PECVD nitride exhibit trap-induced dispersive behavior, which leads to degradation in capacitor linearity at low frequencies, limiting the accuracy in precision analog circuits. While LPCVD oxide results in nondispersive behavior, the high deposition temperature excludes the use of LPCVD dielectrics for MIM capacitors using the standard back-end metal layers as capacitor bottom plates. The latter is preferred in view of the low substrate coupling needed for RF applications. In this work, alternative PECVD dielectrics have been investigated with respect to frequency dependence of voltage linearity, hysteresis, matching, and leakage characteristics. It will be shown that ONO stacks offer a combination of good voltage linearity, absence of dispersive behavior and hysteresis, excellent matching, and low leakage     

Characteristics of thin lanthanum lutetium oxide high-k dielectrics

In this work, we evaluate the thermal stability of thin film lanthanum lutetium oxide (LLO) on silicon deposited using molecular beam epitaxy (MBE). Thin LLO films are capped with TaN and annealed at 700 °C or 900 °C in nitrogen or oxygen ambients. SIMS analysis indicates no La and Lu up diffusion into TaN after annealing. However, after a 900 °C anneal Si is detected in the LLO. SIMS data also suggested growth of interfacial oxide upon anneal. Cross sectional TEM of as deposited films show a sharp high-k/Si-substrate interface with very thin interfacial layer. An increase in the LLO layer thickness, and the interfacial layer thickness between the LLO and the Si-substrate is observed after annealing. Capacitors with LLO dielectrics were also formed using TiN electrode and low leakage is demonstrated for samples annealed at 700 °C. However, a large positive flatband voltage shift and an increase in leakage is observed in LLO capacitors after undergoing 900 °C anneal with a TiN metal gate.     

Inkjet printed thin and uniform dielectrics for capacitors and organic thin film transistors enabled by the coffee ring effect

The deposition of a thin and uniform dielectric layer is required for high performance printed capacitors and thin film transistors (TFTs), however this is difficult to achieve with printing methods. We have demonstrated inkjet-printed dielectrics with a uniform thickness from 70 nm to 200 nm by taking advantage of the coffee ring effect. A high capacitance per unit area of 230 pF/mm² is achieved from capacitors with linear morphologies fully printed onto flexible substrates. We also demonstrate organic TFTs with an average mobility of 0.86 cm²/Vs and a source drain current of 57 μA obtained with a supply voltage of 15 V. This performance was shown to be consistent, with a standard deviation of 15% obtained from hundreds of printed organic TFTs on PET substrates. This consistency was further validated by the production of functional NAND, NOR, AND and OR logic gates. Our results demonstrate that the coffee ring effect, which is usually viewed as undesirable, can enable higher performance in printed electronic devices.     

Thickness measurement of thin oxide layers in MOS capacitors

The validity of the SiO/sub 2/ layer thickness determined from capacitance-voltage measurements in MOS devices is demonstrated by comparison with results obtained by X-ray photoelectron spectroscopy, high-resolution transmission electron microscopy and spectroscopic ellipsometry published elsewhere in the literature.<>     

An on-chip ECC circuit for correcting soft errors in DRAMs withtrench capacitors

A modified error-correcting code that can correct up to two soft errors on each row (word line) in a dynamic random-access memory (DRAM) chip is proposed. Double-bit soft errors frequently occur in DRAM cells with trench capacitors, when charged alpha particles impinge on the intervening space between two vertical capacitors causing plasma shorts between them. The conventional on-chip error-correcting codes (ECCs) cannot correct such double-bit word-line soft errors, which significantly increase the uncorrectable error rate (UER). An ECC circuit that uses an augmented rectangular product code to detect and correct double-bit soft errors is presented. The proposed circuit automatically corrects the addressed bit if it is faulty, and then quickly locates the other faulty bit. A comprehensive study is made to estimate improvements in soft error rate (SER) and mean time to failure (MTTF). The ability of the circuit to correct soft errors in the presence of multiple-bit errors has also been analyzed by combinatorial enumeration     

Analog characteristics of metal-insulator-metal capacitors usingPECVD nitride dielectrics

The frequency dependence of PECVD nitride and LPCVD oxide metal-insulator-metal (MIM) capacitors is investigated with special attention for precision analog applications. At measurement frequencies of 1.0 MHz, nitride MIM capacitors show capacitance linearity close to that of oxide MIM capacitors, indicating potential for precision analog circuit applications. Due to dispersion effects, however, nitride MIM capacitors show significant degradation in capacitor linearity as the frequency is reduced, which leads to accuracy limitations for precision analog circuits. Oxide MIM capacitors are essentially independent of frequency     

有机薄膜电容器替代电解电容器应用分析

分析了有机薄膜电容器的结构特点及发展趋势,并通过典型电路中的电容器应用实例结合电容器的应用性能参数对比分析,总结得出了有机薄膜电容器替代电解电容器的优势。在电源旁路、滤波、电源开关等对耐纹波电流能力、损耗和电容量稳定性要求较高的电路中,有机薄膜电容器可替代钽电解电容器。     

KH550-GO复合栅介质低压氧化物薄膜晶体管

采用旋涂法制备硅烷偶联剂-氧化石墨烯(KH550-GO)新型复合栅介质薄膜,由于栅介质层和沟道层界面处明显的双电层效应,单位面积电容高达2.18×10~(–6)F/cm~2。通过自组装法,借助磁控溅射仪,仅需一次掩膜,即可同时生成晶体管的沟道与源漏电极。利用半导体参数分析仪在室温黑暗的条件下测量该晶体管的电学特性,结果表明,KH550-GO栅介质氧化物薄膜晶体管具有优良的电学性能,其工作电压仅为2 V、饱和电流为580μA、亚阈值摆幅108 m V/dec、开关比4×10~7、场效应迁移率16.7 cm~2·V~(-1)·s~(-1)。     

Simulation of the variability in microelectronic capacitors havingpolycrystalline dielectrics

The scaling down of on-chip microelectronic capacitors presents a considerable challenge for future microelectronic devices. High-permittivity polycrystalline dielectrics such as Ta₂O ₅, SrTiO₃ (STO), or (Ba, Sr)TiO₃ (BSTO), have been considered as a potential replacement for conventional amorphous SiO₂ and SiN_x. The polycrystalline microstructure of these materials may lead to capacitor-to-capacitor variations in charge storage capacity and charge retention. In this letter, a Monte Carlo simulation is used to assess these variations. Results show that as the average crystalline grain size becomes greater than 1% of the capacitor size, variations of 10% in capacitance and between 3-150% in leakage should be expected     

Lifetime investigation and prediction of metallized polypropylene film capacitors

Metallized polypropylene film capacitors (MPPFCs) possess characteristics of high reliabilities and high energy densities, so they are widely used in the pulse power systems. MPPFC prototypes with high voltage and large capacitance are composed of a number of cylindrical MPPFC elements connecting in series or in parallel. The experimental data show that the lifetime of MPPFC prototypes is far shorter than that of MPPFC elements under the same voltage stress.     

Electrical characteristics and reliability properties of metal-oxide-semiconductor capacitors with HfZrLaO gate dielectrics

Metal-oxide-semiconductor (MOS) capacitors incorporating atomic-layer-deposition (ALD) HfZrLaO high-κ gate dielectric were fabricated and investigated. The equivalent oxide thickness (EOT) is 0.68 nm and the gate leakage current density (J_g) is only 9.3 × 10⁻¹ A/cm². The time-dependence dielectric breakdown (TDDB) behavior agrees with the percolation model, and the TDDB characteristics are consistent with the thermochemical E-model for lifetime projection. The experimental results show that the Weibull slopes are almost independent of capacitor area and stress conditions. The field acceleration parameter (γ) and activation energy (ΔH₀) are determined around 5.9-7.0 cm/MV and 0.54-0.60 eV, respectively. At 85 °C, the maximum voltage projected for 10-years TDDB lifetime is 1.87 V.     

Reliability of gate dielectrics and metal–insulator–metal capacitors

In this review paper reliability characterisation methods of SiO₂ as gate dielectric and metal–insulator–metal capacitors with various dielectrics are discussed. It includes the test structure design, the stress and measurement sequences, the raw data analysis and the extrapolation models of measured time to breakdown to lifetimes at operating conditions and targeted product failure rates. For each topic various references are given where further details are described. Especially pitfalls of approaches and problem areas are highlighted.     

Reactively sputtered tantalum pentoxide thin films for integrated capacitors

The aim of this work was to develop a deposition process for a high-dielectric constant tantalum pentoxide for integrated capacitors. Thin films were deposited reactively on glass wafers using a radio-frequency magnetron sputtering cluster tool at various O₂/Ar flow ratios. By using 2 MeV ⁴He⁺ backscattering spectroscopy and X-ray diffraction, the films obtained showed a stoichiometric orthorhombic β-Ta₂O₅ phase at 20% O₂ in the sputtering gas flow. With low-frequency measurements (f=100 kHz), a 200×200-μm² square metal–insulator–metal (MIM) capacitor with copper electrodes and a 340-nm thick dielectric gave a capacitance density of 0.066 μF/cm², with a quality factor (Q) of 650. The value of the relative permittivity (_r) was approximately 25 determined from MIM capacitors of various sizes. The surface roughness of the 376-nm thick oxide film was found to be small: 0.255 nm. The largest measured capacitor (200×200 μm²) gave reasonable results at low frequencies. When the frequency was increased (100 kHz–20 GHz) only for the smaller capacitors (30×30 μm²) the capacitance remained constant. However, the Q values decreased of the smaller capacitors as a function of frequency. Processed tantalum pentoxide MIM capacitors possessed reasonable electrical properties below 2 GHz and good potential for further improvement.     

Tantalum oxide capacitors for GaAs monolithic integrated circuits

The performance of a high-yield tantalum oxide capacitor for use in GaAs monolithic microwave integrated circuits is described. The integral metal-insulator-metal sandwich structure is reactively sputter-deposited at low temperatures, compatible with a photoresist lift-off process, on semi-insulating GaAs substrate. Dielectric constants of 20-25 were achieved in the capacitors fabricated. An initial application of this process as an interstage coupling capacitor for a two-stage preamplifier is given.     

Fringe field corrections for capacitors on thin dielectric layers

An approximate formula is derived which yields the fringe field correction explicitely in terms of the parameters of the electrode configuration for the frequently encountered case of plane parallel electrodes, of which one is circular and the other infinitely large. Other related cases are also discussed. The error is typically of the order of 1%. The formulae are useful in determining the dielectric constants of crystalline platelets.     

Lateral nonuniformity of effective oxide charges in MOS capacitors with Al/sub 2/O/sub 3/ gate dielectrics

The high-frequency Terman's method for interface-trap-density (D/sub it/) extraction is used to examine the lateral nonuniformity (LNU) of effective oxide charges in MOS capacitors. The two-parallel-subcapacitor model is constructed to simulate LNU charges, and it was shown that the value of the found effective D/sub it/ appears negative as the LNU occurs in the gate oxide. This technique was first used to examine the effective oxide charge distribution in Al/sub 2/O/sub 3/ high-k gate dielectrics prepared by anodic oxidation and nitric-acid oxidation. It was found that the LNU effect in Al/sub 2/O/sub 3/ is sensitive to oxidation mechanisms and can be avoided by using an appropriate oxidation process. The proposed technique is useful for the preparation and reliability improvement of high-k gate dielectrics.