SJ/Z 11353-2006《集成电路IP核转让规范》概要

本指导性技术文件是在参照VSIA（Virtual Socket Inter face Alliance）《Virtual Component Tramster Specification Version2．1》的基础上制定的，并得到了VSIA的版权许可。     

传输函数在滤波器综合中的应用

滤波网络传输函数的零点、极点位置对滤波性能起着决定作用。全极点滤波器的所有衰减极点都位于DC和∞处。如果将传输零点放在S面有限频率处,则会形成特殊频率响应：虚轴上（实频）的传输零点,可形成准椭圆函数的陡降幅频响应;而实轴上（虚频）的和复数（实部非零）传输零点则起到类似时延均衡网络的作用,实现线性相位传输响应。在对不同文献关于传输函数的理论表述进行分析后,总结了传输函数、特征函数以及滤波网络综合中的一些重要概念,给出了几种典型函数的极点分布图对比,提供了几种运用特殊的传输零点放置来实现特殊滤波响应的设计应用。     

SJ/Z 11351-2006《用于描述、选择和转让的集成电路IP核属性格式标准》

本指导性技术文件是在参照VSIA（Virtual Socket Interface Alliance）《Virtual Component Attributes （VCA） With Formats for Profiling,Selection, and Transfer Standard Version 2.2》的基础上制定的,并得到了VSIA的版权许可.     

集成电路的电磁兼容测试

近年来,集成电路的频率越来越高,集成的晶体管数目越来越多,集成电路的电源电压越来越低,加工芯片的特征尺寸进一步减小,越来越多的功能,甚至是一个完整的系统都能够被集成到单个芯片之中,这些发展使芯片级电磁兼容显得尤为重要。现在,集成电路生产商正努力改进他们的产品以满足电磁兼容规范,降低电磁发射和增强抗干扰能力。     

Substrate Optimization for Integrated Circuit Antennas

The reciprocity theorem and integral equation techniques are employed to determine the properties of integrated-circuit antennas. The effect of surface waves is considered for dipole and slot elements on substrates. The radiation and bandwidth of microstrip dipoles are optimized in terms of substrate thickness and permittivity.     

混合集成电路用的封装材料

首先介绍混合集成电路封装技术的发展，然后讨论混合集成电路封装材料的选择及其依据，最后介绍新的混合集成电路封装材料。     

New Challenges for Integrated Circuit Solutions

Integrated circuit solutions have been one of the enabling technologies, contributing to the success of wireless communications. As the focus of the new generation is moving towards higher bandwidths and new services and applications, challenges for the integrated circuit solutions are ever growing. Development focus has shifted from component design and optimization towards significant system oriented content captured both in the hardware platform and supporting software. This integrated approach challenges existing development models, and affects other disciplines related to wireless system development. This paper explores major challenges for integrated circuit solutions emerging from the system-oriented approach.     

通信技术的发展与集成电路和集成光路(上)

通过简要回顾微电子与集成电路技术的成长历程和介绍微光子技术及其集成化芯片(集成光路)的发展趋势，分析了当前微电子与集成电路技术所要解决的关键问题，以及尚处于少年阶段的微光子与集成光路技术要面对的难题，进而探讨未来通信技术与产业的发展对集成电路与集成光路的要求。     

集成电路电磁兼容测试PCB设计

PCB设计为集成电路电磁兼容测试过程中的一个重要环节,对测试结果的精确度有很大影响,并且与常规PCB设计又有比较大的差异.为提高集成电路电磁兼容测试数据的精准度,基于ICEMC测试标准中对PCB设计的要求,对测试PCB设计中的问题进行了研究分析及解决方法验证,给出了三种屏蔽方法设计方案,明确了过孔间距约束的计算方法,提出去耦电容选型原则及I/0负载匹配方法.通过典型测试案例,从PCB结构设计、布局及布线三个方面进行了详细阐述.旨在为IC研发人员和电磁兼容检测人员提供指导和参考.     

单片集成锁相环的实用宏模型

本文提出了一个能在ＳＰＩＣ通用电路分析程序上运行的单片集成锁相环ＬＭ５６５的宏模型。宏模型引出脚与实陆器件一一对应，较好地模拟了ＬＭ５６５各个引起的输出波形及外部元件对其性能的控制，使之能实际应用到由ＬＭ５６５构成的各种电路计算机辅助分析中。     

集成电路ESD设计验证技术

传输线脉冲(TLP)测试是当前电路设计工程师研究ESD保护器件特性和进行ESD加固设计的有力工具.分析了ESD应力作用下MOSFET的工作原理,指出精确测试保护器件或电路在ESD大电流应力下的I-V特性曲线,提取特征参数,将有利于ESD加固设计的一次成功;通过对典型TLP测试波形的分析,将TLP试验与器件的大电流响应建立联系;最后对扩散电阻和nMOSFET的TLP典型I-V特性进行了分析,并给出了实际的设计参数.     

BiCMOS多功能闪光集成电路

本文介绍了一种用于装饰、灯光控制、广告制作等方面的多功能闪光集成电路,简述了电路的基本特点以及电路的结构,版图设计思想和工艺制作。电路使用3～5V电源,满负载输出电流可达15mA。     

模拟集成电路的测试节点选择

如何寻求一个最佳的测试节点或测试矢量集是模拟集成电路的故障诊断中的重要问题。该文提出了一种基于可测性测度计算的测试节点选择方法。利用行列式判决图,可以有效而准确地求得被测电路传输函数的符号表达式和计算出其可测性测度。该方法完全消除了由数字方法引入的不可避免的舍入误差,并能处理中、大规模的集成电路.     

混合集成电路的外引线键合技术

混合集成电路外引线键合的方式很多。与混合集成电路的内引线键合不同，外引线键合时，键合丝的1端在管壳的引线柱上。因此，管壳外引线金属镀层的结构、镀层材料、键合丝的性能和键合工艺因素都将影响混合电路外引线键合的质量。本文主要对Au丝球焊、Au丝点焊、SiAl丝超声焊等不同的键合工艺及其对应的金属学系统进行研究，并对其结果进行比较。采用Au丝点焊工艺键合混合电路外引线的效果最佳。     

集成电路生产中成品率的有效管理

本文分析了在集成电路制造过程中,使用的基础材料、设备、工艺技术所产生的污染粒子,随机缺陷对IC产品成品率的影响。并主要介绍了从经典学习曲线概念中推导出来的成品率提高模型已被用于追踪产品成品率的提高,该模型建立在能优先迅速解决影响成品率诸多问题的基础上。实际成品率与模型化成品率的比较充分证明了成品率提高模型的实际意义。     

微封装微波集成电路(MPMIC)

本文介绍了微封装微波集成电路的特点及国内外发展概况。重点叙述了集成压控振荡器、集成宽带放大器和集成电控衰减器国外及13所的发展水平以及MPMIC的工艺和封装。     

MOS Integrated Circuit Reliability

This paper presents information on the reliability of MOS integrated circuits based on p-channel enhancement-mode transistors, and describes their failure modes and mechanisms. The principal failure mechanisms were ion migration at the surface and oxide shorting. The results of experimental studies of the effects of variations in construction, processing, and levels of stress are presented, and are compared with other available information on MOS integrated circuit reliability. The failure rate for commercially available complex MOS arrays is on the order of 0.001 to 0.01 per 1000 h of operating life at 125°C for arrays containing approximately 600 p-channel transistors. This corresponds to a failure rate on the order of 5 × 10?6 to 5 × 10?5 per equivalent gate per 1000 h. The effects of device complexity, operating temperature, and other factors are discussed. A reliability prediction equation for MOS integrated circuits is derived from available information. An overall activation energy for functional failure mechanisms of approximately 5 kcal/mole (?0.2 eV/molecule) is considered applicable to typical MOS integrated circuits. Thus, the failure rate of MOS devices operated at 50°C ambient temperature can be predicted to be on the order of 10?6 to 10?5 per equivalent gate per 1000 h.     

An Externally Trimmed Integrated DC Current Regulator Insensitive to Conducted EMI

This paper introduces a new integrated dc current regulator using external resistive trimming, which presents a high degree of immunity against conducted electromagnetic interference (EMI). While classic topologies generate erratic bias currents that are totally different from the expected value once EMI is injected into the circuit, this new topology succeeds in producing the same fixed dc current, whether EMI is present or not. Extra filtering requiring small on-chip capacitors ensures that the ripple on the output current due to the interference remains at a very low value.     

Direct-Charge-Transfer Pseudo-N-Path SC Circuit Insensitive to the Element Mismatch and Opamp Nonidealities

A novel pseudo-N-path switched-capacitor circuit is described. Its center frequency is insensitive to element mismatch as well as to the finite gain and bandwidth of the opamps used. In this new architecture, the charges from the input source to the output are not transferred by an opamp; rather the opamp is used only as a buffer. The performance of the circuit is superior to that of a regular pseudo-N-path structure.