A 32-b RISC/DSP microprocessor with reduced complexity

This paper presents a new 32-b reduced instruction set computer/digital signal processor (RISC/DSP) architecture which can be used as a general purpose microprocessor and in parallel as a 16-/32-b fixed-point DSP. This has been achieved by using RISC design principles for the implementation of DSP functionality. A DSP unit operates in parallel to an arithmetic logic unit (ALU)/barrelshifter on the same register set. This architecture provides the fast loop processing, high data throughput, and deterministic program flow absolutely necessary in DSP applications. Besides offering a basis for general purpose and DSP processing, the RISC philosophy offers a higher degree of flexibility for the implementation of DSP algorithms and achieves higher clock frequencies compared to conventional DSP architectures. The integrated DSP unit provides instruction set support for highly specialized DSP algorithms. Subword processing optimized for DSP algorithms has been implemented to provide maximum performance for 16-b data types. While creating a unified base for both application areas, we also minimized transistor count and we reduced complexity by using a short instruction pipeline. A parallelism concept based on a varying number of instruction latency cycles made superscalar instruction execution superfluous     

Multimedia Signal Processors: An Architectural Platform with Algorithmic Compilation

Novel algorithmic features of multimedia applications and advances in VLSI technologies are driving forces behind the new multimedia signal processors. We propose an architecture platform which could provide high performance and flexibility, and would require less external I/O and memory access. It is comprised of array processors to be used as the hardware accelerator and RISC cores to be used as the basis of the programmable processor. It is a hierarchical and scalable architecture style which facilitates the hardware-software codesign of multimedia signal processing circuits and systems. While some control-intensive functions can be implemented using programmable CPUs, other computation-intensive functions can rely on hardware accelerators.To compile multimedia algorithms, we also present an operation placement and scheduling scheme suitable for the proposed architectural platform. Our scheme addresses data reusability and exploits local communication in order to avoid the memory/communication bandwidth bottleneck, which leads to faster program execution. Our method shows a promising performance: a linear speed-up of 16 times can be achieved for the block-matching motion estimation algorithm and the true motion tracking algorithm, which have formed many multimedia applications (e.g., MPEG-2 and MPEG-4).     

A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation

As DSP (Digital Signal Processing) applications become more complex, there is also a growing need for new architectures supporting efficient high-level language compilers. We try to synthesize a new DSP processor architecture by adding several DSP processor specific features to a RISC core that has a compiler friendly structure, such as many general-purpose registers and orthogonal instructions. The synthesized digital signal processor supports single-cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping capabilities in addition to ordinary RISC instructions. The compiler for the new architecture is quickly implemented by developing a code-converter that modifies the assembly codes that are generated by the RISC compiler. The performance effects of adding each of these as well as all the combined features are evaluated using seven DSP-kernel benchmarks, a QCELP vocoder, and an MPEG video decoder. The effects of CPU clock frequency change due to the addition of these features are also considered. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.     

多核DSP编程技术研究

数字信号处理器（DSP）是对数字信号进行高速实时处理的专用处理器。当前,基于单核结构的嵌入式处理器越来越不能满足日益增长的数据处理应用方面的要求,单纯的增加单个处理器的处理速度更会带来难以接受的能耗。多核嵌入式结构已成为解决这一问题的有效途径,也使整个系统只用DSP搭建成为可能,但同时也为如何开发充分利用多核结构的应用...     

嵌入式Flash CISC/DSP微处理器的研究与实现

本文研究一种新的既具有微控制器功能,又有增强DSP功能的高性能微处理器的实现架构.在统一的增强CISC指令集下,我们将基于哈佛和寄存器-寄存器结构的微处理器模块和单周期乘法/累加器、桶形移位寄存器、无开销循环及跳转硬件支持模块、硬件地址产生器等DSP功能模块以及嵌入式Flash Memory和指令队列缓冲器有机的集成起来,在统一架构下通过单核实现CISC/DSP微处理器,有效地提高了处理器的性能.该微处理器采用0.35μm CMOS工艺实现,芯片面积为25mm².在80M工作频率下,动态功耗为425mW,峰值数据处理能力可达80MIPS.该处理器核可满足片上系统(SOC)对高性能处理器的需求.     

计算高度密集型应用在异构多核DSP上的运行方法研究

研究实现了计算高度密集型应用在异构多核DSP上运行的方法.即利用存储在RISC核外设总线上的FLASH中的应用程序,通过异构多核DSP目标板加电,自动加载到RISC核RAM执行,该应用程序将计算高度密集型应用的DSP程序加载到DSPs核上,并利用RISC核向DSPs核点火执行.主要介绍了异构多核DSP中的RISC核和DSP核的复位、启动方法,DSP核的多种冗余降级工作模式,详细分析了RISC核控制DSP核的原理及操作方法.提出的运行方法完整有效,为相关的研究人员打下了良好的基础.     

在OpenRISC中实现CRC32并行计算

随着RISC CPU/DSP处理速度的提高,使得使用微码程序来实现原来只有用ASIC才能实现的高速通信链路上的数据适配和处理成为可能.该文介绍了一个开源的RISC处理器体系结构,并为了使之适用于通信处理,在其中增加了一个CRC32的并行计算单元,用以支持用微码指令计算CRC,并行计算宽度为32 bits.对所提的CRC32并行计算方法进行了详细阐述.     

双内核嵌入式处理器OMAP5910及其在第三代无线终端领域的多媒体应用

OMAP5910是一种新型的双内核嵌入式处理器 ,文章介绍了该处理器的主要特点及其硬件和软件架构。重点阐述了OMAP5910处理器在第三代无线终端领域的多媒体应用 ,最后给出了OMAP5910在嵌入式语音系统中的应用实例。     

基于OMAP的3G无线终端处理器系统的硬件研究与开发

在深入理解ARM和TMSC320C5000在参与基于OMAP5910的3G无线终端的多媒体应用平台硬件系统设计基本原则的基础上,文章画出一个硬件系统原理图和印刷电路板图;各种功能模块进行测试和调试;完成与CPLD相关的硬件语言设计和调试,在QuartusII软件下用VerilogHDL编写;在掌握Linux操作系统及嵌入式操作系统的移植和开发及Linux下的驱动程序开发的基础上,完成DSP、Camera、触摸屏等底层驱动程序的开发;完成Microwindow下顶层用户界面和JPEG等应用程序的开发,和Linux驱动程序开发。     

在OMAP3530平台实现AVS解码器

详细讨论了OMAP架构的双核通信机制,分析了Codec Engine,DSPlink,CMEM等核心模块。然后实现了一种基于OMAP3530开发平台的AVS视频解码系统,实现了ARM处理器接收网络数据和显示图像,DSP处理器解码AVS码流。在Linux环境下将AVS视频解码器移植到3530开发板中,在分辨率D1下达到25 f/s(帧/秒)。     

采用Trimedia/Nexperia DSP的流结构模式实现G.723.1实时语音编解码

G．723．1协议是将音频信号压缩到5．3Kb／s和6．3Kb／s2种码率的音频编解码协议，主要应用在多媒体通信中的音频压缩。介绍一种基于Trimedia／Nexperia DSP的流结构TSSA(Trimedia Streaming Software Architecture)实现应用在可视电话中的G．723．1实时语音编解码。     

Signaling for multimedia conferencing in 4G: the case of integrated 3G/MANETs

Fourth-generation wireless systems are composed of coexisting and cooperating legacy and new networks. Mobile ad hoc networks are examples of new networks. They have several attractive characteristics and are gaining more and more momentum. Their integration with legacy third-generation networks is now being contemplated. Multimedia conferencing is the basis of a wealth of applications, including video conferences, multiparty games, and distance learning. Signaling is the central nerve of multimedia conferencing. It establishes, modifies, and tears down multimedia conferencing applications. This article is devoted to the signaling aspects of multimedia conferencing in 4G and focuses on the specific case of integrated 3G/MANETs. It reviews the standard 3G architecture and the emerging architectures for MANETs. This review shows that none of them is suitable for integrated 3G/MANETs. We propose a new architecture based on application-level clusters and conference gateways. We have implemented a prototype using the session initiation protocol (SIP) technology.     

Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications

This paper describes a new architecture for JAVA-based, interactive multimedia applications. A hardware implementation of a Java Virtual Machine (JVM) is proposed, which allows the direct execution of Java bytecode. In a single clock cycle, up to 3 bytecode instructions can be decoded and executed in parallel using a RISC pipeline. A splitable 64-bit ALU implementation addresses demanding processing requirements of typical multimedia signal processing schemes. The on-chip caches are adapted to the specific data structures of the JVM. The proposed architecture supports execution of multiple Java threads in parallel. An implementation of basic building blocks of the processor with a standard-cell library provides an estimate of 150 MHz clock-speed for a 0.35 m 3 metal layer CMOS process. With a size of less than 10 mm² needed for the core logic, it is possible to integrate multiple JVMs together with larger cache memories on a single chip. Based on these results, we discuss various performance aspects of JAVA for use in future multimedia terminals.     

3G移动终端的发展趋势

移动终端的体系结构主要包括通信、操作系统、内存、应用、多媒体、安全和电源管理等子系统。3G终端的发展趋势将主要支持如视频通信、在线浏览、即时通信、互动游戏、高速下载等更多种类和更丰富的数据业务应用，计算速度更快，存储能力更强。而目前作为核心功能的通信将会变为从属地位，成为移动终端的标准配置。     

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part II: Application Programming

Two representative multimedia applications—AAC and H.264/AVC decoders on the parallel architecture core (PAC) SoC are introduced in the second part of the two introductory papers. The applications have been programmed on the PACDSP core and the PAC SoC to demonstrate the high-performance, low-power DSP computations and the effectiveness of the dynamic voltage and frequency scaling (DVFS) capability on the heterogeneous multicore SoC. First, techniques to exploit data- and instruction-level parallelisms existing in the application kernels are described for performance optimizations on the clustered VLIW architecture of PACDSP with the distributed register organization. Next, two variation techniques of asymmetric programming model are introduced by examples of decoders. Then, the energy efficiency of the programmable multimedia SoC is demonstrated using an innovative power-aware H.264/AVC decoder. Finally, a DVFS-aware framework for soft real-time video playback is provided by extending the power-aware decoding scheme. The work provides practical references of realizing multimedia applications on PAC SoC suitable for rich-function and resource constraint portable devices.     

A framework for reconfigurable computing: task scheduling andcontext management

Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the design process and achieve optimal exploitation of the architectural features of the system. Task scheduling and context (configuration) management become very critical issues in achieving the high performance that digital signal processing (DSP) and multimedia applications demand. This article proposes a strategy to automate the design process which considers all possible optimizations that can be carried out at compilation time, regarding context and data transfers. This strategy is general in nature and could be applied to different reconfigurable systems. We also discuss the key aspects of the scheduling problem in a reconfigurable architecture such as MorphoSys. In particular, we focus on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations     

G.729协议在TMS320C6211上的实现

ITU—T提出基于CS—ACELP算法传输速率为8kbit／s的G．729协议，该协议可以用作如PHS（个人手持电话系统）、比特率低于64kbit／s的可视会议等多媒体服务，也可以作为有效利用传输能力的多路复用器。概要介绍了G．729协议的算法结构，对G．729协议在TMS320C6211DSP上的实现进行了研究。     

基于双核处理器的无线多媒体终端设计

描述了如何利用TI OMAP芯片设计无线多媒体终端.在介绍了OMAP芯片的双核处理器结构后,阐述了该无线多媒体终端的硬件设计、软件设计,并给出两个示范性多媒体应用实例.测试证明,该终端具有高性能和低功耗的特点,能满足未来无线多媒体业务对手持设备的需求.     

基于OMAP的车载多媒体处理平台的DSP端软件设计

OMAP芯片是TI公司推出的具有双核结构的微处理器，目前已经广泛地应用于无线通信领域。针对OMAP的结构特点，平台的ARM端运行Montavista Linux操作系统，主要进行无线网络通信和人机界面交互等任务；DsP端运行DSP／BIOS操作系统，用于音频编解码等实时数值运算。DSP端应用程序在RF6框架的基础上，着重对数据处理模块、底层驱动模块等进行了设计。该平台具有很好的扩展性，目前已经开发了MP3下载播放、IP电话用户终端等车载应用。     

Multimedia processors

This paper describes large-scale-integration programmable processors designed for multimedia processing such as real-time compression and decompression of audio and video as well as the generation of computer graphics. As the target of these processors is to handle audio and video in real time, the processing capability must be increased tenfold compared to that of conventional microprocessors, which were designed to handle mainly texts, figures, tables, and photographs. To clarify the advantages of a high-speed multimedia processing capability, we define these chips as multimedia processors. General-purpose microprocessors for workstations and personal computers (PCs) use special built-in hardware for multimedia processing, so the multimedia processors described include these modified general-purpose microprocessors. After reviewing the history of programmable processors, we classify multimedia processors into five categories depending on their basic architecture. The categories are reduced instruction set computer (RISC) microprocessors for workstations, complex instruction set computer microprocessors for PCs, embedded RISCs, low-power digital signal processors (DSPs), which are mainly used for mobile communications devices, and media processors that support PCs for multimedia applications. These five classes are then grouped into two: microprocessors with a multimedia instruction set and highly parallel DSPs. An architectural comparison between these two groups on the basis of Moving Picture Experts Group decoding applications is made, and the advantages and disadvantages of each class are clarified. Future processors, including “system on a chip,” and their applications are also discussed