一种改进的层次化SOCs并行测试封装扫描单元

 测试封装是实现SOC内部IP核可测性和可控性的关键,而扫描单元是测试封装最重要的组成部分.然而传统的测试封装扫描单元在应用于层次化SOCs测试时存在很多缺点,无法保证内部IP核的完全并行测试,并且在测试的安全性,功耗等方面表现出很大问题.本文提出一种改进的层次化SOCs测试封装扫描单元结构,能够有效解决上述问题,该结构的主要思想是对现有的扫描单元进行改进,实现并行测试的同时,通过在适当的位置增加一个传输门,阻止无序的数据在非测试时段进入IP核,使得IP核处于休眠状态,保证了测试的安全性,实现了测试时的低功耗.最后将这种方法应用在一个工业上的层次化SOCs,实验分析表明,改进的测试封装扫描单元比现有扫描单元在增加较小硬件开销的前提下,在并行测试、低功耗、测试安全性和测试覆盖率方面有着明显的优势.     

A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling

The increasing test application times required for testing system-on-chips (SOCs) is a problem that leads to higher costs. For modular core based SOCs it is possibly to employ a concurrent test scheme in order to lower the test application times. To allow each core to be tested as a separate unit, a wrapper is inserted for each core, the scan chains at each core are configured into a fixed number of wrapper chains, and the wrapper chains are connected to the test access mechanism. A problem with concurrent testing is that it leads to higher power consumption as several cores are active at a time. Power consumption above the specified limit of a core or above the limit of the system will cause damage and must be avoided. The power consumption must be controlled both at core level as well as on system level. In this paper, we propose a reconfigurable power conscious core wrapper that we include in a preemptive power constrained test scheduling algorithm. The advantages with the wrapper are that the number of wrapper chains at each core can dynamically be changed during test application and the possibility, through clock gating, to select the appropriate test power consumption for each core. The scheduling technique produces optimal solutions in respect to test time and selects wrapper configurations in a systematic manner while ensuring the power limits at core level and system level are not violated. The wrapper configurations are selected such that the number of wrapper configurations as well as the number of wrapper chains at each wrapper are minimized, which minimizes the wrapper logic as well as the total TAM routing. We have implemented the technique and the experimental results show the efficiency of our approach. The research is supported by the Swedish Foundation on Strategic Research (SFS) under the Strategic Integrated Electronic Systems Research (STRINGENT) program.     

一种新的嵌入式Linux实时调度算法

针对现有实时调度算法在实时性能上的不足,提出了一种新的实时任务分类调度算法,根据实时任务的到达情况进行分类,划分为周期任务和非周期任务,并对不同类型的实时任务使用不同的改进的实时调度算法.通过实验,证明此算法与现有实时调度算法相比,综合实时性能有了很大程度的提高.     

A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips

This paper deals with the design of SOC test architectures which are efficient with respect to required ATE vector memory depth and test application time. We advocate the usage of a TestRail Architecture, as this architecture, unlike others, allows not only for efficient core-internal testing, but also for efficient testing of the circuitry external to the cores. We present a novel heuristic algorithm that effectively optimizes the TestRail Architecture for a given SOC by efficiently determining the number of TestRails and their widths, the assignment of cores to the TestRails, and the wrapper design per core. Experimental results for four benchmark SOCs show that, compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.     

A Note on System-on-Chip Test Scheduling Formulation

While many different formulations of the embedded core test scheduling problem (ECTSP) have been proposed in test literature recently, a single unified presentation of ECTSP in terms of conventional scheduling patterns has been lacking. There exists a large body of literature on multi-processor scheduling which can be directly applied to ECTSP; in this paper the author presents an introduction to scheduling notation and demonstrates the mapping between many important test scheduling problems like power-constrained, precedence constrained, and defect-oriented scheduling to conventional multi-processor job scheduling problems. Two examples are presented to illustrate this mapping. This unified presentation should make the existing body of knowledge in Operations Research scheduling research easily accessible to test engineers and test automation tool developers.     

Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design

Temperature affects not only the performance but also the power, reliability, and cost of the embedded system. This paper proposes a temperature-aware task allocation and scheduling algorithm for MPSoC embedded systems. Thermal-aware heuristics are developed, and a temperature-aware floorplanning tool is used to reduce the peak temperature and achieve a thermally even distribution while meeting real time constraints. The paper investigates both power-aware and thermal-aware approaches to the task allocation and scheduling. The experimental results show that the thermal-aware approach outperforms the power-aware schemes in terms of maximal and average temperature reductions. To the best of our knowledge, this is the first MPSoC task allocation and scheduling algorithm that takes temperature into consideration.

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一种嵌入式信号处理软件构件测试框架

嵌入式系统在保障雷达信号处理高可靠性和高实时性要求的同时,其硬件耦合度高和处理数据量大的问题给嵌入式测试的自动化推进带来了挑战。为提高嵌入式信号处理软件的测试效率,提出了一种构件级测试的自动化框架,该框架通过解析构件的测试用例表产生测试数据,调用驱动镜像,并根据测试脚本自动执行测试,评估测试结果,最终生成测试报告,实现测试全流程的自动化。文中给出了该框架应用于某产品构件测试的实际效果,缩短近一半的人工耗时,验证了其正确性及有效性。     

带等待时间约束并行机调度问题的Copula分布估计算法

本文针对一类带等待时间约束的不相关并行机调度问题,提出了一种基于Copula函数的分布估计算法.该算法以同类订单工件数与总工件数的比值为变量,对每台机器构造了一个Copula函数,进而建立了优势种群的概率模型.基于概率模型通过采样生成子代个体编码向量组,保留了父代种群的相对位置信息.从理论上分析了所提出算法的时间复杂度,其随工件个数的增加呈对数增长.通过基于实例的数值仿真以及与已有算法的比较验证了所提算法的有效性和鲁棒性.     

一种基于全局调度的改进CLOS结构及其调度算法

现有的关于Clos交换结构的调度算法在关注调度性能的同时,逐渐忽略了其在硬件实现上的复杂度。该文根据一款星载交换芯片的设计实现,提出了一种改进型的Clos结构,且在此基础上设计了一种硬件实现简单且能实现极大匹配的调度算法。     

3D NoC测试规划研究与实现

针对3D NoC资源内核的测试,采用NoC重用测试访问机制和XYZ路由方式,建立功耗模型,并通过云进化算法将IP核的测试数据划分到各TAM上进行并行测试,从而降低了测试时间。实验以ITC 02标准电路作为测试对象,其结果表明,文中方法可以有效地减少测试时间,提高了测试效率。     

A Novel Collision Sup ervision and Avoidance Algorithm for Scalable MAC of Vehicular Networks

In order to meet low-latency and ultra-reliable requirements on safety services in vehicular networks, this paper proposes a novel Collision supervision and avoidance (CSA) algorithm for the contention based scalable media access control protocol. The two-dimensional Markov chain model of adaptive backoff state transition criterion in CSA has been built, which could efficiently match the backoff states of nodes to the dynamic changes of vehicular networks. The scalable transmissions can be achieved through supervised trend and matching backoff mechanisms with three adaptive backoff modes. The packet transmit probabilities for the backoff modes have been derived with the theoretical result of the enhanced throughput. The simulation results show the remarkable scalability performance such as normalized throughput >0.92, PDR >86％ and delay <6.5ms even in the high-density and high-mobility environment.     

一种信号个数估计方法及其在测频中的应用

本文介绍一种高精度的数字测频算法———根MUSIC算法。通过分析发现,该算法在低信噪比(0 dB)的情况下,仍能得到高精度的频率估计值,其频率分辨率也比DFT高。然而,在电子侦察中要应用该方法进行测频,关键是首先要确定接收信号的个数。根据协方差矩阵特征值的大小分布特点,本文提出了差分中值法来确定信号个数,该方法的性能优于MDL准则。计算机仿真验证了该方法的可行性和稳健性。     

一种新型超宽带穿墙雷达运动目标跟踪成像算法

近场区域的非接触式穿墙目标跟踪成像探测是超宽带脉冲雷达在火灾救援、安全保卫、城市巷战以及生命威胁等方面的一个重要应用。基于超宽带脉冲雷达的边界散射变换和直接散射波形提取的边界估计算法(SEABED)由于其不适用于穿墙条件下运动目标的成像与跟踪的情况,该文结合SEABED算法的成像原理,提出回波时延差关系曲线概念从而利用三角定位原理和坐标转换实现运动目标的成像与跟踪。文中提出的算法假设在近场条件下,针对运动目标场景建立系统模型,通过成像结果和速度值的同时估计,对墙体背后的运动目标的边界和轨迹进行有效估计。仿真结果表明,该算法能够弥补墙体对目标回波的影响,精确度高,达到穿墙目标跟踪成像探测的目的。