一个全集成的CMOS脉冲超宽带发射机

本文给出了一个低功耗、全集成的CMOS脉冲式超宽带发射机电路的设计和流片测试结果,其集成了亚纳秒脉冲发生器、脉冲位置调制(PPM)器和天线驱动电路等,可支持多种调制方式并产生最高达1Gp/s的超宽带脉冲序列.设计采用数字驱动信号上升沿触发的新型反馈结构脉冲发生器,可产生稳定的脉冲信号.通过可调的脉冲宽度和PPM调制步长,设计提供了工艺参数和温度变化的补偿手段.     

A fully integrated differential impulse radio transmitter

This paper presents a fully integrated differential impulse radio transmitter for ultra-wideband (UWB) applications. The design features low power dissipation, simple hardware, and a precise differential pulse shape. The transmitter employing the time hopping pulse position modulation (TH-PPM) scheme supports eight simultaneous users’ access with 2.5-ns hopping time allocated in a frame time of 20 ns. A differential 5th-derivative Gaussian pulse generator (PG) is designed for the first time to regulate the pulse shape so as to automatically satisfy the Federal Communications Commission (FCC) spectrum mask. The transmitter in a 1.8-V 0.18-μm CMOS process is realized in an IC area of 629 μm × 797 μm for its all digital circuit design. The measured digital pulse width of the TH-PPM pulse train is 2.5 ns and the measured 5th-derivative Gaussian pulse has a peak-to-peak amplitude of 154 mV and a pulse width of 820 ps. The power dissipation of the transmitter is 23 mW.     

A fully integrated CMOS direct-conversion transmitter front-end for WiMAX

A naturally commutated six-pulse cycloconverter working in the inverting mode is used to feed power to a single phase AC motor at 400 Hz. The motor is connected at the input side of the cycloconverter while the three-phase mains is connected at its output. Three-phase mains feeds power to the input side of the cycloconverter which is arranged as a tuned load at 400 Hz. The effect of the single-phase induction motor on system performance is discussed. The principle of voltage and frequency control for proper operation of the induction motor is presented. The results are experimentally verified.     

0.34 THz高速无线通信发射机芯片设计

基于0.13μm Si Ge Bi CMOS工艺,设计了一个应用于0.34 THz高速通信系统的4路集成相控阵发射机芯片。该芯片集成了21.25 GHz的锁相环(PLL)频率源、4倍频器、4路威尔金森(Wilkinson)功分网络,每一路相控阵通道包括85 GHz功率放大器、模拟移相器、20 Gbps二进制启闭键控(OOK)调制器、4倍频器以及2×2片载天线阵列。针对系统各个模块进行了测试和分析,并且对系统方向图进行了仿真。仿真结果表明,该相控阵系统能在E面实现±12°的角度扫描,3 d B波束宽度为11.9°,系统有效等向辐射功率(EIRP)为12 d Bm。该集成相控阵发射机芯片的面积为8 mm×4.3 mm。     

A fully integrated SiGe receiver IC for 10-Gb/s data rate

A silicon germanium (SiGe) receiver IC is presented here which integrates most of the 10-Gb/s SONET receiver functions. The receiver combines an automatic gain control and clock and data recovery circuit (CDR) with a binary-type phase-locked loop, 1:8 demultiplexer, and a 2 ⁷-1 pseudorandom bit sequence generator for self-testing. This work demonstrates a higher level of integration compared to other silicon designs as well as a CDR with SONET-compliant jitter characteristics. The receiver has a die size of 4.5×4.5 mm2 and consumes 4.5 W from -5 V     

A fully integrated low power PAM multi-channel UWB transmitter

A new transmitter for ultra-wideband (UWB) impulse radio is described in this paper. The new UWB transmitter implements a low power Gaussian shaping filter to reduce the side-lobe in the frequency domain. A simple pulse amplitude modulation (PAM) circuit is used to keep the power consumption low. The proposed architecture features the simple design, low-power operation, and enables the pulse-shape generation for a multi-channel UWB. The core layout size is only 0.2 mm². The simulation results show that the generated signals satisfy the FCC spectrum mask, and the average power consumption is <1.97 mW for the 1.8 V supply voltage. Pulses are transmitted at a PRF (pulse repetition frequency) of 40.5 MHz in 500 MHz bandwidth channels equally spaced within the 3.1–10.6 GHz UWB. This transmitter is designed and fabricated in a 0.18-μm CMOS process.     

A fully integrated 24-GHz phased-array transmitter in CMOS

This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 /spl Omega/, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to- ratio of 23 dB with raw beam-steering resolution of 7/spl deg/ for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm /spl times/ 2.1 mm of die area.     

低功耗输出脉冲幅度和频谱可调的超宽带发送机设计

A 3-5 GHz low power BPSK modulated impulse radio UWB transmitter is implemented in 0.13μm CMOS technology. In this design the amplitude and spectrum of the output impulse are both tunable to solve the special problem in IR-UWB, where it is difficult to control the spectrum. Measurement results indicate that, by changing the control bits in the gain control circuit and differential circuit, the 3-step peak-to-peak voltage amplitudes are 240, 170 and 115 mV and the center frequency of the impulse can be tuned from 3.2 to 4.1 GHz. A power controlled output buffer is designed to drive the antenna. The total power consumption is only 4.44 mW when transmitting a baseband signal of 100 MHz. The chip area is 1.2 × 1.4 mm^2.     

A fully integrated BPSK amplitude and spectrum tunable transmitter for IR-UWB system

A 3-5 GHz low power BPSK modulated impulse radio UWB transmitter is implemented in 0.13 μm CMOS technology. In this design the amplitude and spectrum of the output impulse are both tunable to solve the special problem in IR-UWB, where it is difficult to control the spectrum. Measurement results indicate that, by changing the control bits in the gain control circuit and differential circuit, the 3-step peak-to-peak voltage amplitudes are 240, 170 and 115 mV and the center frequency of the impulse can be tuned from 3.2 to 4.1 GHz. A power controlled output buffer is designed to drive the antenna. The total power consumption is only 4.44 mW when transmitting a baseband signal of 100 MHz. The chip area is 1.2×1.4 mm2.     

A novel fully integrated transmitter front-end with high power-added efficiency

A novel fully integrated transmitter front-end with a simple structure is proposed to obtain both high power-added efficiency (PAE) and a compact RF-front structure. To have all these characteristics, a novel antenna operating as a radiator, a harmonic tuning circuit, and an output matching network of the power amplifier is proposed. Therefore, the direct integration of the output of the power amplifier and antenna can be achieved without any impedance transformers. From the measured results and fabrication, it is shown that the proposed transmitter front-end provides high PAE of 67.5% and compact and integrated RF-front structure by the size reduction of 43% compared with the conventional class-F active antenna for high PAE.     

A self-calibrating Hall sensor IC with direction detection

A monolithic wheel speed sensor integrated circuit based on Hall effect is presented. Speed and motion direction of magnetic encoder wheels or ferromagnetic target wheels are detected. Two specific amplitudes of the magnetic input signal are detected as well. A two-wire current output directly linked to the input signal frequency indicates speed. Direction information and detection of specific amplitudes of the magnetic input signal are encoded in its output pulsewidth. It features a strictly differential sensing principle, a new direction detection algorithm, and a dynamic self-calibrated offset compensation. The integrated circuit is manufactured in a 0.6-/spl mu/m BiCMOS process, enhanced by bipolar transistors with increased breakthrough voltage.     

A low-power NMOS transmit/receive IC filter for PCM telephony

A very low-power single chip NMOS implementation of the transmit and receive PCM filters used in telephony applications is described. The circuit utilizes doubly-terminated switched capacitor low-pass and high-pass filters and meets accepted requirements without trimming. The filters have low idle-channel noise, consume only 20 mW of power, and are realized in a small area of silicon. Design of the overall architecture, the individual filter sections, and the operational amplifiers in NMOS technology is described.     

A low-power 2.4-GHz transmitter/receiver CMOS IC

A 2.4-GHz CMOS receiver/transmitter incorporates circuit stacking and noninvasive baseband filtering to achieve a high sensitivity with low power dissipation. Using a single 1.6-GHz local oscillator, the transceiver employs two upconversion and downconversion stages while providing on-chip image rejection filtering. Realized in a 0.25-/spl mu/m digital CMOS technology, the receiver exhibits a noise figure of 6 dB and consumes 17.5 mW from a 2.5-V supply, and the transmitter delivers an output power of 0 dBm with a power consumption of 16 mW.     

A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-/spl mu/m CMOS

A fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK) transmitter and a receive frequency synthesizer for GSM. The entire transmitter/synthesizer is fully integrated in 0.35-/spl mu/m CMOS and consumes 17.4 and 12 mW from 2.5 V in the transmit and receive modes, respectively, including an on-chip voltage-controlled oscillator. The circuit meets GSM specifications on modulation accuracy in transmit mode, and measured phase noise from the closed-loop PLL is -148 dBc/Hz and -162 dBc/Hz, respectively, at 3- and 20-MHz offset. Worst case spur at 13-MHz offset is -77 dBc.     

GaAs MESFET laser-driver IC for 1.7-Gbit/s lightwave transmitter

GaAs monolithic integrated circuits for modulating junction lasers (laser drivers) have been developed for a 1.7-Gb/s lightwave communication system. The modulation currents can be varied continuously from a few mA up to 50 or 100 mA, depending on the types of laser drivers. It has been demonstrated that devices of the low-current type are capable of driving a 50-Ω load with a 50-mA modulation current with pulse rise and fall times (10% to 90%) less than 200 ps, and the high-current devices are capable of driving a 25-Ω load with up to 100-mA modulation current with pulse rise and fall times less than 250 ps. Nearly temperature-independent performance has been achieved from 0°C to 70°C. The laser drivers are also capable of providing output DC currents proportional to the duty cycle of input data for the purpose of duty-cycle-independent feedback control of junction lasers. The circuit designs and performance of these devices are described     

A 0.25-/spl mu/m CMOS OPLL transmitter IC for GSM and DCS applications

A single-chip CMOS global system for mobile communications/digital cellular system dual-band offset phase-locked loop (OPLL) transmitter is presented in this paper. This chip includes a quadrature modulator and an OPLL modulation loop. Except for the loop filter and high-power voltage-controlled oscillator (TX VCO), everything is integrated into this chip to form a dual-band transmitter. This transmitter integrated circuit is fabricated in a 0.25-mum CMOS process. The current consumption without the TX VCO is approximately 23 mA under 2.7-V power supply for both bands. The measured rms and peak phase errors for Gaussian minimum shift-keying (GMSK) modulated signals are approximately 1deg and 2.4deg, respectively. The measurements show comparable performance to its BiCMOS counterparts     

A fully integrated 40-Gb/s clock and data recovery IC with 1:4DEMUX in SiGe technology

In this paper, a fully integrated 40-Gb/s clock and data recovery (CDR) IC with additional 1:4 demultiplexer (DEMUX) functionality is presented. The IC is implemented in a state-of-the-art production SiGe process. Its phase-locked-loop-based architecture with bang-bang-type phase detector (PD) provides maximum robustness. To the authors' best knowledge, it is the first 40-Gb/s CDR IC fabricated in a SiGe heterojunction bipolar technology (HBT). The measurement results demonstrate an input sensitivity of 42-mV single-ended data input swing at a bit-error rate (BER) of 10^-10. As demonstrated in optical transmission experiments with the IC embedded in a 40-Gb/s link, the CDR/DEMUX shows complete functionality as a single-chip-receiver IC. A BER of 10^-10 requires an optical signal-to-noise ratio of 23.3 dB     

A 0.18-/spl mu/m CMOS offset-PLL upconversion modulation loop IC for DCS1800 transmitter

A DCS1800 offset-phase-locked-loop upconversion modulation loop integrated circuit (IC) fabricated in a 0.18-/spl mu/m CMOS technology is presented in this paper. This IC operates at 2.8-V supply voltage with a current consumption of 36 mA. The measured root-mean-square and peak phase errors of the Gaussian minimum shift keying (GMSK) transmission signal are 1.6/spl deg/ and 4/spl deg/, respectively. It is shown that such circuits can be implemented in CMOS process with current dissipation and performance comparable to BiCMOS chips. Advantages of upconversion modulation loop and design issues of I/Q modulators are also described.     

Low-power MicroVrms noise neural spike detector for implantable interface microsystem device

In this paper, an ultra-low-power and low-noise spike detector is proposed for massive integration in the implantable multichannel brain neural recording device. The detector circuit with nonlinear energy operator (NEO) algorithms achieves the spike detecting from action potential including complex noise. The spike detector circuit consists of a differentiator with a fully-differential structure and a multiplier based on CMOS translinear using sub-threshold technique. The differentiator has the steepness of a transmission function with frequency +20 dB/dec, frequency response from 10 Hz to 10.5 kHz. The linear range of multiplier is from −0.9 V to 0.9 V at V_DD = ±1.65 V. The spike detector is implemented in 0.35 μm technology with fully-CMOS process. One detector die size is 0.0187 mm² and its total current consumption of 825 nA. As is demonstrated by measured results, the proposed circuit has detected the instantaneous energy of the input real spike signals well, which the noise of small than 218 μV_rms over a nominal bandwidth of 500–10.5 kHz.