BiCMOS例相器延迟特性的计算与分析

本文对ＢｉＣＭＯＳ倒相器延迟特性进行了系统研究，在分析比较ＭＯＳ与双极器件及其组成电路不同状态下的工作特点基础上，得到ＢｉＣＭＯＳ倒相电路在小注入、大注入和集电极寄生电阻等不同限制条件下的延迟时间的解析关系式，结果表明该模型具有近似于ＳＰＩＣＥ数值模拟精度，为各类高性能ＢｉＣＭＯＳ电路的优化设计与分析提供了理论依据．     

TFT有源矩阵液晶显示系统设计

本文论述了ＴＦＴ有源矩阵液晶显示系统的设计原理，包括驱动电路（专用ＣＭＯＳ电路ＢＤＤ１００１，ＢＤＤ２００１）和控制电路（同步信号发生电路，图像信号产生电路和背电极电路），实现计算机模拟电视信号驱动液晶显示系统。     

BiCMOS倒相器延迟特性的计算与分析

本对ＢｉＣＭＯＳ倒相器延迟特性进行了系统研究，在分析比较ＭＯＳ与双极器件及其组成电路不同状态下的工作特点基础上，得到ＢｉＣＭＯＳ倒相电路在小注入，大注入和集电极寄生电阻等不同限制条件下的延迟时间的解析关系式，结果表明该模型具有近似于ＳＰＩＣＥ数值模拟精度，为各类高性能ＢｉＣＭＯＳ电路的优化设计与分析提供了理论依据。     

采用混合模式晶体管(BMHMT)构成低温BiCMOS集成电路

本文介绍采用与ＣＭＯＳ工艺完全相容的双极／ＭＯＳ混合模式晶体管（ＢＭＨＭＴ）构成新型的低温ＢｉＣＭＯＳ集成电路．理论分析表明该电路与ＣＭＯＳ相比，在电压摆幅相同，静态功耗相近的条件下，具有更大的驱动能力，尤其在较低的工作电压下，其特点更加突出．我们用统一的标准和相同芯片面积设计了３９级带负载的ＢｉＣＭＯＳ和ＣＭＯＳ环形振荡器．实验样品经室温和低温平均门延迟时间测试，表明在相同工作电压下ＢｉＣＭＯＳ优于ＣＭＯＳ．若两种电路都采用ＳＯＩ结构，预计ＢｉＣＭＯＳ可以获得更好的结果     

亚微米BiCMOS工艺技术

ＢｉＣＭＯＳ是双极的速度和驱动能力与ＣＭＯＳ的高密度和低功耗的结合。考虑到功耗原因，ＢｉＣＭＯＳ器件主要以ＣＭＯＳ为主。因此，双极器件通常并入ＣＭＯＳ核心工艺流程。当器件尺寸减小时，双极和ＣＭＯＳ技术显得愈发相似。本文例举了０．８μｍ和０．５μｍ的技术论点，ＢｉＣＭＯＳ电路与ＣＭＯＳ相比，成本稍有增加，但其性能提高一倍。     

电话机所用CMOS模拟电路设计技术

面对日益增长的电话机市场的需求,我们从一九九四年就开始了电话机拨号电路和液晶显示驱动电路的设计和生产。到现在为止,已经研制开发成功了Ｗ9145、ＣＳＣ91341、ＣＳＣ91340、Ｗ91560、ＣＳＣ9202、ＣＳＣ9302、ＣＳＣ9246、ＣＳＣ71098、ＣＳＣ1616、ＣＳＣ1613Ａ、ＣＳＣ1616Ａ等多个电话机ＣＭＯＳ集成电路。为了提高电话机拨号电路和液晶显示驱动电路的设计一次成功率,有必要对这些电路的ＣＭＯＳ模拟部分的逻辑及ＬＡＹＯＵＴ版图进行系统分析和整理,使之系统化和模块化,这对于以后继续开发电话机拨号电路和液晶显示驱动电路的后续…     

先进CMOS复位保护电路的研究

介绍了一种用于ＣＭＯＳ数字电路的上电复位和低压保护电路，该上偏置电路、比较放大电路、延迟产生电路和驱动电路四部分组成，具有复位时间短、响应速度快、控制精度高、抗噪声能力强、结构简单、功耗低等优点，已成功地应用于ＡＳＩＣ电路中。还给出电路和的计算机模拟结果。     

CMOS电路芯片ESD保护电路设计技术的发展

本文简要地回顾了ＣＭＯＳ电路芯片上ＥＳＤ保护电路设计技术发展概况，给出了在中小规模、大规模及超大规模各阶段的ＣＭＯＳ电路芯片上ＥＳＤ保护电路的主流技术，双寄生的ＳＣＲ结构ＶＬＳＩ ＣＭＯＳ芯片上ＥＳＤ保护电路的最新设计技术，就其ＥＳＤ保护原理、设计技术及取得的成果做了较详细分析和探讨。对于研制高密度、高速度的ＶＬＳＩ ＣＭＯＳ电路。开展高ＥＳＤ失效阈值电压，小几何尺寸及低ＲＣ延迟时间常数保护电路的     

自对准硅化物CMOS／SOI技术研究

在ＣＭＯＳ／ＳＩＭＯＸＳＯＩ电路制作中引入了自对准钴（Ｃｏ）硅化物（ＳＡＬＩＣＩＤＥ）技术，研究了ＳＡＬＩＣＩＤＥ工艺对ＳＯＩＭＯＳＦＥＴ单管特性和ＣＭＯＳ／ＳＯＩ电路速度性能的影响．实验表明，采用ＳＡＬＩＣＩＤＥ技术能有效地减小ＭＯＳＦＥＴ栅、源、漏电极的寄生接触电阻和方块电阻，改善单管的输出特性，降低ＣＭＯＳ／ＳＯＩ环振电路门延迟时间，提高ＣＭＯＳ／ＳＯＩ电路的速度特性．     

集成电路中栅介质膜的C－V测试误差分析及其修正模型

通过具有各种串联电路的ＭＯＳ电容的分析测试表明：串联电阻引起ＭＯＳＣ－Ｖ特性畸变、失真，并与介质膜电容大小有关；串联电容使ＭＯＳＣ－Ｖ特性严重不稳定；而当存在电容和电阻并联的串联电路时，即使串联电路中的电阻高达１ｋΩ以上，只要其并联的电容远大于介质膜电容，这个串联电路的影响就可以忽略不计。也测试分析了硅衬底参数和测试环境对ＭＯＳＣ－Ｖ特性的影响。指出了改善测试分析准确性的各种有效途径。提出了ＭＯＳＣ－Ｖ特性的串联电阻修正模型。即：存在串联电阻效应的判据；ＭＯＳＣ－Ｖ特性失真的判据；串联电阻计算公式、电容修正公式及ＭＯＳＣ－Ｖ修正过程。举例说明修正模型编程的实际应用：超薄栅氧化层ＭＯＳＣ－Ｖ特性的修正；ＣＭＯＳ电路中，Ｐ阱中ＭＯ５电容Ｃ－Ｖ特性的修正。     

互连线网时延估算的一种有效算法

本文提出一种基于传递函数递推和系数匹配的互连线网时延估算法,该算法用二极点模型逼近互连线网的传递函数,仅通过计算某一频率点上的传递函数,就可利用导出的解析公式或拟合的经验公式进行快速时延估算,不必进行复杂的分量计算,算例表明,对于各个门限值,其计算结果均与ｓｐｉｃｅ计算的时延值发接近,计算量也比通常基于高阶分量计算的算法大为减少,在计算效率和模拟精度两方面得到较好折衷,对于互连线网时延估算具有实用     

考虑串扰效应的性能驱动全局布线器研究

提出了利用符号化矩计算模型进行性能驱动的多级布线方法.通过在模式布线阶段利用符号化矩计算模型,快速得到电路的高阶矩,并根据计算结果,采用合理的代价函数对时延串扰等性能指标进行预估,进而指导布线.实验结果显示,该算法在串扰优化方面得到较大的提高,布线结果兼顾了时延优化和信号波形质量优化.     

Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow

This paper studies the prediction of interconnect delay in an industrial setting. Industrial circuits and two industrial field-programmable gate-array (FPGA) architectures were used in this paper. We show that there is a large amount of inherent randomness in a state-of-the-art FPGA placement algorithm. Thus, it is impossible to predict interconnect delay with a high degree of accuracy. Furthermore, we show that a simple timing model can be used to predict some aspects of interconnect timing with just as much accuracy as predictions obtained by running the placement tool itself. Using this simple timing model in a two-phase timing driven physical synthesis flow can both improve quality of results and decrease runtime. Next, we present a metric for predicting the accuracy of our interconnect delay model and show how this metric can be used to reduce the runtime of a timing driven physical synthesis flow. Finally, we examine the benefits of using the simple timing model in a timing driven physical synthesis flow, and attempt to establish an upper bound on these possible gains, given the difficulty of interconnect delay prediction.     

基于信道接入的通信端到端传输时延分析

文中利用信道接入技术对通信端到端的传输时延进行计算,首先将时延分为传输设备传输时延、数据帧长度时延、线路时延,然后计算通信端到端的传输时延,以获得整个通信信号时序序列的计算方法。利用信道接入技术,采用计算模型,计算时延序列中单组信号的出现概率,在此基础上计算出通信端到端的传输时延。最后开展仿真实验,实验结果表明信道接入能够减少计算误差。     

一种Farrow结构数字延时滤波器的设计

普通数字延时滤波器虽然结构简单,但系数计算过程复杂,在延时参数快速变化时,系数更新速度无法满足实时性要求,在工程应用上受限制。采用Farrow结构数字延时滤波器能够更加灵活高效地进行分数延时滤波,延时参数改变时,无需重新计算滤波器系数,更容易在现场可编程门阵列(FPGA)上实现。介绍了一种Farrow结构数字延时滤波器,提出采用基于对称结构的滤波器系数求解方法,并经过加权优化,获得最终Farrow滤波器的系数。系数计算过程中,通过对设计所得Farrow滤波器延时精度和误差的分析,调整加权因子的取值和滤波器阶数,进而提高延时精度。计算机仿真结果证明了加权对称系数求解Farrow滤波器系数方法的有效性和实用性。     

Discharge-path-based antenna effect detection and fixing for X-architecture clock tree

Antenna effect is a phenomenon in the plasma-based nanometer process and directly influences the manufacturing yield of VLSI circuits. Because antenna-critical metal wires have sufficient charges to damage the thin gate oxides of the clock input ports connected by a clock tree, the standard cells or IPs cannot be driven by the clock source synchronously. For a given X-architecture clock tree that connects n clock sinks, we consider the antenna effect in the clock tree and propose a discharge-path-based antenna effect detection method. To fix the antenna violations, we use the jumper insertion technique recommended by foundries. Furthermore, we integrate the layer assignment technique to reduce the inserted jumper and via counts. Differing from the existing works, the delay of vias is considered in delay calculation, and a wire sizing technique is applied for clock skew compensation after fixing the antenna violations. Experimental results on benchmarks show that our algorithm runs in O(n²) to averagely insert 48.21% less jumpers and reduce 20.35% in vias compared with other previous algorithms. Moreover, the SPICE simulation further verifies the correctness of the resulting clock tree.     

Fast Interconnect and Gate Timing Analysis for Performance Optimization

Static timing analysis is a key step in the physical design optimization of VLSI designs. The lumped capacitance model for gate delay and the Elmore model for wire delay have been shown to be inadequate for wire-dominated designs. Using the effective capacitance model for the gate delay calculation and model-order reduction techniques for wire delay calculation is prohibitively expensive. In this paper, we present sufficiently accurate and highly efficient filtering algorithms for interconnect timing as well as gate timing analysis. The key idea is to partition the circuit into low and high complexity circuits, whereby low complexity circuits are handled with efficient algorithms such as total capacitance algorithm for gate delay and the Elmore metric for wire delay and high complexity circuits are handled with sign-off algorithms. Experimental results on microprocessor designs show accuracies that are quite comparable with sign-off delay calculators with more than of 65% reduction in the computation times     

Delay propagation effect in transistor gates

Wide VLSI transistors suffer additional switching delays due to signal propagation when passing through the resistive gate polysilicide. We model and evaluate this resistive effect and define an analytical expression in terms of extra propagation term. This delay can be reduced by breaking up a single wide transistor into smaller transistors connected and driven in parallel. This work develops expressions for deciding how many parallel transistors should be employed so as to limit the additional delay caused by the resistive polysilicide to within desired bounds. The expressions are validated by comparing calculated delay results with those from HSPICE simulations     

利用耦合时延增强激光混沌系统安全性能研究

安全性是混沌通信中的重要问题。基于一个外光反馈半导体激光器驱动两个互耦合激光器的混沌通信系统,研究激光混沌系统中反馈时延与耦合时延特征,并应用龙格-库塔法进行动态仿真。重点分析了当调节一些可控参数(耦合时延和驱动强度)时,能够改变两耦合激光器输出自相关函数中反馈时延和耦合时延幅值的差异,以此掩藏反馈时延,从而得出更优载波。仿真结果说明利用耦合时延可以增强激光混沌系统的安全性。最后给出了在优化载波后系统同步质量的讨论。     

Noise measurements in two-beam interferometers excited bysemiconductor lasers with non-Lorentzian line shapes

An experimental study of phase-induced intensity noise is presented for the case of a Mach-Zehnder interferometer driven by a non-Lorentzian line shape semiconductor laser. The important scales of the noise spectrum in the coherent regime are shown to be related not only to the interferometer differential delay but also to the relaxation-oscillation frequency. It is shown that the periodic nulls in the noise spectrum from a two-beam interferometer locked in quadrature can be washed out at frequencies near the relaxation oscillations of the semiconductor laser. However, when the relaxation-oscillation frequency far exceeds 1/(interferometer differential delay), the classical deep notch at 1/(interferometer differential delay) is recovered and can be used to improve the system signal-to-noise ratio