关于NO氮化SiO2超薄栅介质膜的研究

研究了采用ＮＯ快速热氮ＳｉＯ２ 方法制备超薄栅介质并初步制备出约５ｎｍ超薄栅的ＭＯＳ电容和约６ｎｍ超薄 ＮＭＯＳＦＥＴ,ＮＯ氮化改善了超薄ＳｉＯ２膜的性能。     

SiGe／Si异质结构MOS器件栅介质技术研究

本文研究ＳｉＧｅ／Ｓｉ异质结构ＭＯＳ器件栅介质制备技术，采用等离子体增强化学汽相淀积（ＰＥＣＶＤ）方法低温制备电学特性优良的薄栅介质薄膜，并应用于ＳｉＧｅ／Ｓｉ异质结构器件研制，试制成功ＳｉＧｅ／Ｓｉ异质结构ＰＭＯＳ和ＮＭＯＳ实验性器件．     

短沟道CMOS／SOI器件加固技术研究

通过大量辐照实验分析了采用不同工艺和不同器件结构的薄膜短沟道ＣＭＯＳ／ＳＩＭＯＸ器件的抗辐照特性，重点分析了Ｈ２－Ｏ２合成氧化和低温干氧氧化形成的薄栅氧化层、ＣｏＳｉ２／多晶硅复合栅和多晶硅栅以及环形栅和条形栅对ＣＭＯＳ／ＳＩＭＯＸ器件辐照特性的影响，最后得到了薄膜短沟道ＣＭＯＳ／ＳＩＭＯＸ器件的抗核加固方案．     

RTP改善超薄SiO2膜特性的研究

超薄ＳｉＯ２膜经快速热处理后，电特性得到了改善，本研究用超薄ＲＴＰＳｉＯ２膜制作ＭＯＳ电容，ｈ－ＮＭＯＳＦＥＴ中介栅介质层及ＦＬＯＴＯＸ－Ｅ＾２ＰＲＯＭ中作隧道氧化层，取得了一些实验结果，从结果中可以看出具有实有价值。     

掺HCI栅氧化对MOS结构电特性的影响

研究了栅氧化时掺ＨＣｌ的硅栅ＭＯＳＦＥＴ的ＤＤＳ－ＶＧＳ特性，阈电压和界面态。结果发现，ＨＣｌ掺入栅介质，可使ＩＤＳ－ＶＧＳ曲线正向漂移，ＰＭＯＳＦＥＴ阈电压绝对值减小，ＮＭＯＳＦＥＴ阈电压增大，Ｓｉ／ＳｉＯ２界面态密度下降，采用氯的负电中心和Ｓｉ／ＳｉＯ２界面硅悬挂键的键合模型对实验结果进行了解释。     

凹槽栅MOSFET凹槽拐角的作用与影响研究

短沟道效应是小尺寸ＭＯＳＦＥＴ中很重要的物理效应之一，凹槽栅ＭＯＳＦＥＴ对短沟道效应有很强的抑制能力，通过对凹槽栅ＭＯＳＦＥＴ结构，特性的研究，发现凹槽拐角对凹槽栅ＭＯＳＦＥＴ的阈值电压及特性有着显著的影响，凹槽拐角处的阈值电压决定着整个凹槽栅ＭＯＳＦＥＴ的阈值电压，凹槽拐角的曲率半径凹槽ＭＯＳＦＥＴ一个重要的结构参数，通过对凹槽拐角的曲率半径，源漏结深及沟道掺杂浓度进行优化设计，可使凹槽栅ＭＯＳ     

掺HCl栅氧化对MOS结构电特性的影响

研究了栅氧化时掺ＨＣｌ的硅栅ＭＯＳＦＥＴ的ＤＤＳ－ＶＧＳ特性、阈电压和界面态．结果发现，ＨＣｌ掺入栅介质，可使ＩＤＳ－ＶＧＳ曲线正向漂移，ＰＭＯＳＦＥＴ阈电压绝对值减小，ＮＭＯＳＦＥＴ阈电压增大，Ｓｉ／ＳｉＯ２界面态密度下降。采用氯的负电中心和Ｓｉ／ＳｉＯ２界面硅悬挂键的键合模型对实验结果进行了解释。     

注F栅介持抗电离辐射损伤机理

对含Ｆ ＭＯＳ结构的抗电离辐射特性和机理进行了系统研究。其结果表明：Ｆ减少工艺过程引入栅介持的Ｅ　’中心缺陷和补偿Ｓｉ／ＳｉＯ２悬挂键的作用,将导致实始氧化物电荷和界面态密度的下降;栅ＳｉＯ２中的Ｆ主要以Ｆ离子和Ｓｉ－Ｆ结键的方式存在;含Ｆ栅介质中部分Ｓｉ－Ｆ键替换Ｓｉ－Ｏ应力键而使Ｓｉ／ＳｉＯ２界面应力得到释放,以及用较高键能的Ｓｉ－Ｆ键替换Ｓｉ－Ｈ弱键的有益作用是栅介质辐射敏感降低的根本原因;     

VLSI介质材料的研究动态和发展方向

本文阐述了当前在ＣＭＯＳ和ＤＲＡＭ中，栅氧化层、ＩＭＤ、ＤＲＡＭ电容器三个方面所用的低介质常数和高介质常数材料的研究动态以及发展方向。     

双栅MOSFET的研究与发展

具有特殊结构的双栅ＭＯＳＦＥＴ是一种高速度、低功耗ＭＯＳＦＥＴ器件,符合未来集成电路发展的方向。文章介绍了多种双栅ＭＯＳＦＥＴ的结构、优点,以及近年来国内外对双栅ＭＯＳＦＥＴ的研究成果。     

Modeling of distributed parasitics in power FETs

A distributed circuit analysis of power FETs accounting for the lateral source parasitic impedance in addition to the lateral drain and gate parasitic impedances is presented. Both a numerical solution and an exact analytic solution are derived. Using the exact analytic solution, approximate equivalent circuits are derived for FETs of short gate width for two common types of boundary conditions. When the gate and drain terminals are located on opposite sides of the distributed FET, the lateral source parasitic impedance can be represented for short gate width FETs by an equivalent circuit with a negative series impedance in series with the source terminal. The practical consequences on parameter extraction for device modeling are discussed. The availability of an exact analytic solution for the distributed FET should also assist with the synthesis of traveling wave FETs.     

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II–VI Gate Insulators

This paper presents the successful use of ZnS/ZnMgS and other II–VI layers (lattice-matched or pseudomorphic) as high-k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO _x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO _x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.     

Au/TiN/WSi-gate self-aligned GaAs MESFETs using rapid thermal annealing method

Au/TiN/WSi-gate self-aligned GaAs MESFETs were fabricated using the rapid thermal annealing method to reduce the gate resistance of the FETs. The gate resistance Rg was 4.2 ? (Lg=1.5 ?m, Wg=400 ?m), just 1/20 of that of the WSi-gate FET. The maximum frequency of oscillation fmax of the Au/TiN/WSi-gate FETs was improved to be about twice that of WSi-gate FETs.     

Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs

The performances of accumulation-mode and inversion-mode multigate FETs are compared. The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode FETs.     

Investigation of Si/SiGe-based FET geometries for high frequencyperformance by computer simulation

The high frequency performance of n-channel Si/SiGe-based FETs is investigated by computer simulation. Using a two-dimensional hydrodynamic model, devices having gate lengths down to 0.1 μm are examined. Self-aligned heterojunction MOSFETs are found to offer the best performance in terms of cut-off frequency and available voltage gain. Schottky gate heterojunction FETs have the highest transconductance in this study, but simulations confirm that this is because of the close proximity of the channel to the gate. Depletion mode MOS gate devices are also considered and a large parameter space is explored     

An intrinsic delay extraction method for Schottky gate field effect transistors

This letter reports a new method for extracting the intrinsic transit delay associated with the carrier transport under the gate of field-effect transistors (FETs). With this method, the parasitic charging time is ruled out by the de-embedding used to strip the pad parasitics. Therefore, the intrinsic transit delay and the drain delay associated with the extended depletion region toward drain electrode can be separated without the influence of the parasitic charging time, as proven by an analysis of short-channel InP-based high electron mobility transistors. The method is applicable to any type of Schottky-gate FETs and could be helpful for studying the effective carrier velocity in the gate region of FETs.     

Dual-Gate Multiple-Channel ZnO Nanowire Transistors

We report on conventional multichannel ZnO nanowire field-effect transistors (FETs) operating in one device in a dual-gate mode. Our FETs were prepared by assembling ZnO nanowires on a Si substrate using an optimized dielectrophoresis technique with bottom-gate and top-gate FET structures. We observed that the enhancement of the electrical characteristics in FETs with top-gate mode operation results from a thinner gate oxide and top-gate geometry compared with FETs with bottom-gate mode operation. It was also verified that surface passivation strongly affected the electrical performance of ZnO nanowire FETs.     

Four-State Sub-12-nm FETs Employing Lattice-Matched II–VI Barrier Layers

Three-state behavior has been demonstrated in Si and InGaAs field-effect transistors (FETs) when two layers of cladded quantum dots (QDs), such as SiO _x -cladded Si or GeO _x -cladded Ge, are assembled on the thin tunnel gate insulator. This paper describes FET structures that have the potential to exhibit four states. These structures include: (1) quantum dot gate (QDG) FETs with dissimilar dot layers, (2) quantum dot channel (QDC) with and without QDG layers, (3) spatial wavefunction switched (SWS) FETs with multiple coupled quantum well channels, and (4) hybrid SWS–QDC structures having multiple drains/sources. Four-state FETs enable compact low-power novel multivalued logic and two-bit memory architectures. Furthermore, we show that the performance of these FETs can be enhanced by the incorporation of II–VI nearly lattice-matched layers in place of gate oxides and quantum well/dot barriers or claddings. Lattice-matched high-energy gap layers cause reduction in interface state density and control of threshold voltage variability, while providing a higher dielectric constant than SiO₂. Simulations involving self-consistent solutions of the Poisson and Schrödinger equations, and transfer probability rate from channel (well or dot layer) to gate (QD layer) are used to design sub-12-nm FETs, which will aid the design of multibit logic and memory cells.     

The effect of gate recess profile on device performance ofGa0.51In0.49P/In0.2Ga0.8Asdoped-channel FET's

The effect of gate recess profile on device performance of Ga_0.51In_0.49P/In_0.2Ga_0.8As doped-channel FETs was studied. In the experiment, Ga_0.51In _0.49P/In_0.2Ga_0.8As doped-channel FETs (DCFET's) using triple-recessed gate structure were compared with devices using single-recessed and double-recessed gate structures. It is found that triple-recessed gate approach provides higher breakdown voltage (35 V) than single-recessed (16 V) and double-recessed gate (28 V) approaches. This is attributed to the larger aspect ratio in the triple-recessed gate structure. A unified method to calculate the breakdown voltages of MESFETs, HEMTs and DCFETs (or MISFETs) of any given arbitrary recessed gate profile was proposed and used to explain the experimental results