An InAs channel heterojunction field-effect transistor with hightransconductance

A report is presented on an InAs channel field-effect transistor (FET) based on AlGaSb/InAs/AlSb/AlGaSb structures grown by molecular-beam epitaxy. Excellent pinch-off characteristics have been obtained. An FET with a gate length of 1.7 μm showed transconductances ranging from 460 mS/mm (at V_ds=0.5 V) to 509 mS/mm (at V_ds=1 V) and a K factor of 1450 mS/Vmm (at V_ds=1 V) at room temperature     

Combined effects of hot-carrier stressing and ionizing radiation inSiO2, NO, and ONO MOSFETs

N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V_t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V _t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V _t shift due to irradiation of the hot-electron stressed (stressing with V_d=V_g=6.5 V) device was less than that of the unstressed device     

Direct-coupled FET logic circuits on InP

A process technology for direct-coupled FET logic (DCFL) circuits on InP substrates, based on enhancement-mode InGaAs/InAlAs heterostructure-insulated-gate FETs (HIGFETs) is discussed. Its performance was demonstrated by fabricating 11- and 19-stage ring oscillators. The circuits were fabricated on undoped lattice-matched heterostructures grown by molecular beam epitaxy (MBE), using a refractory-gate process with self-aligned sidewalls to achieve a lightly-doped-drain (LDD) structure. For a gate length of 1.2 μm, with V_dd=2 V, the best propagation delay observed was 23 ps/stage, with associated power of 2.2 mW/stage     

Effects of localized interface defects caused by hot-carrier stressin n-channel MOSFETs at low temperature

Hot-carrier stressing was carried out on 1-μm n-type MOSFETs at 77 K with fixed drain voltage V_d=5.5 V and gate voltage V_g varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation ΔG_m and threshold voltage shift ΔV_t, do not occur at the same V_g. As well, ΔK_t is very small for the V_g <V_d stress regime, becomes significant at V_g≈V_d, and then increases rapidly with increasing V_g, whereas ΔG_m has its maximum maximum in the region of maximum substrate current. The behavior is explained by the localized nature of induced defects, which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress     

Dynamic changes in characteristics of a-Si transistors during fastpulsed operation

The switching time of a-Si thin-film transistors (TFTs) was measured. During pulsed operation there are dynamic changes of threshold voltage (V_t) and gate capacitance which occur mostly on a time scale ranging from microseconds to milliseconds. These can be qualitatively explained in terms of the fraction of the induced channel charge which is trapped in deep states in the semiconductor, and its spatial distribution. The value of V_t can decrease by a much as 3 V during a pulse and also depends on the duty cycle. In pulsed operation, V_t is always less than the static value; hence, the current output will be higher than calculated from the static characteristics and will depend on the duty cycle. The effective mobility remains nearly constant with changes of operating cycle. The change in source-gate capacitance confirms the inward diffusion of the trapped charge     

A new two-mode channel FET (TMT) for super-low-noise and high-powerapplications

A super-low-noise two-mode channel FET (TMT) with high- and plateau-shaped transconductance (g_m) characteristics has been developed. It has two electron transport modes against the applied gate voltage (V_gs). That is, the electrons mainly drift in a highly doped channel region at a shallow V_gs. A plateau g_m region and the maximum g_m were achieved at a V_gs range of -0.25~+0.5 V and 535 mS/mm, respectively. The minimum noise figure and associated gain for the TMT were superior in the low-drain-current (I_ds) region and nearly equal in the middle and high I_ds region to those of an AlGaAs/InGaAs pseudomorphic HEMT fabricated using the same wafer process and device geometry     

Multigigahertz CMOS dual-modulus prescaler IC

A low-power CMOS dual-modulus (divide-by-128/129) prescaler IC is described. The IC has been fabricated with symmetric CMOS technology that optimizes simultaneously the characteristics of both the p-channel and n-channel transistors for low-power-supply-voltage operation. Two different gate oxide thicknesses of 175 and 100 Å have been used. The best prescalar fabricated with 175-Å gate oxide functions at 2.06 GHz with 25-m W power consumption (L_eff=0.5 μm; V_dd=3.5 V). Preliminary results for prescalars fabricated with 100-Å gate oxide show that 4.2-GHz operation is possible (L_eff=0.4 μm; V _dd=3.5 V). Power-supply voltage as low as 1.7 V can be used for the prescalar to function at 1 GHz with a power consumption of only 4 mW     

The effect of substrate bias on hot-carrier damage in NMOS devices

Hot-carrier stressing carried out as a function of substrate voltage on 2-μm NMOS devices under bias conditions V_d =8 V and V_g=5.5 V is discussed. The time power-law dependence of stressing changes as a function of substrate bias (V_b), having a power-law gradient of 0.5 for V_b=0 V and 0.3 for V_b=-9 V. Investigation of the type of damage resulting from stressing shows that at V_b=0 V, interface state generation results, while at V_b=-9 V, the damage is mostly by charge trapping. Measurements of the gate current under these two substrate bias conditions show that the gate electron current increases by over two orders of magnitude upon application of a strong back bias. It is suggested that the electron trapping arises from this enhanced gate electron current under large substrate voltage conditions     

A high-speed and highly uniform submicrometer-gate BPLDD GaAsMESFET for GaAs LSIs

The authors present formation conditions for ion-implanted regions of a GaAs buried p-layer lightly doped drain (BPLDD) MESFET that can improve short-channel effect, V_th uniformity, and FET operating speed, simultaneously. For 0.7-μm gates, a Mg⁺ dose of 2×10¹² cm^-2 at 300 keV and a Si⁺ dose of 2×10¹² cm^-2 at 50 keV are suitable for the p layer and n' layer, respectively. A σV _th of 7 mV is realized. Gate-edge capacitance of the 0.7-μm-gate BPLDD that consists of both overlap capacitance and fringing capacitance is successfully reduced to 0.5 fF/μm, which is about 50% of that of a non-LDD buried p-layer (BP) FET. Another parasitic capacitance due to the p-layer was found to have less effect on the speed than the gate-edge one. Consequently, the gate propagation delay time of the BPLDD can be reduced to 15 ps at power dissipation of 1 mW/gate, which is about 65% of that of a BP. Applying the 0.7-μm-gate BPLDD to 16-kb SRAMs, the authors have obtained a maximum access time of less than 5 ns with a galloping test pattern     

The influence of gate edge shape on the degradation in hot-carrierstressing of n-channel transistors

The hot-carrier properties of planar and graded gate structures (upturning of the gate edge in the gate overlap region) of n-MOS transistors were examined. It was found that the type of degradation suffered by each type of device depends on the shape of the gate edge. This is interpreted in terms of the degree of gate control of the gate over the region in which the damage takes place in the different devices. The nongraded gate (NGG) devices degrade chiefly by a V_t shift, whereas the graded gate (GG) devices show a pronounced transconductance decay, with practically no V_t shift. It is suggested that the damage is situated in the gate overlap region, and that the different degradations result from a weaker field control of the gate over the degraded region leading to a series resistance type of effect in the case of the GG structure. This is supported by two-dimensional simulations     

A 4 Mb NAND EEPROM with tight programmed Vtdistribution

Described is a 5-V-only 4-Mb (512K×8 b) NAND EEPROM (electrically erasable programmable ROM) with tight programmed threshold voltage (V_t) distribution, controlled by a novel program-verify technique. A tight programmed V_t distribution width of 0.8 V for the 4 Mb cell array is achieved. By introducing a compact row-decoder circuit, a die size of 7.28 mm×15.31 mm is achieved using 1.0 μm design rules. A unique twin p-well structure has made it possible to realize low-power 5 V-only erase/program operation easily and to achieve 100 K-cycle endurance     

A new technique for measuring MOSFET inversion layer mobility

An experimental technique for accurately determining both the inversion charge and the channel mobility μ of a MOSFET is presented. With this new technique, the inversion charge is measured as a function of the gate and drain voltages. This improvement allows the channel mobility to be extracted independent of drain voltage V_DS over a wide range of voltages (V_DS=20-100 mV). The resulting μ(V_GS) curves for different V_DS show no drastic mobility roll-off at V _GS near V_TH. This suggests that the roll-off seen in the mobility data extracted using the split C- V method is probably due to inaccurate inversion charge measurements instead of Coulombic scattering     

A multiple-state memory cell based on the resonant tunneling diode

The device consists primarily of several molecular-beam-epitaxy (MBE-) grown GaAs/(AlGa)As resonant tunneling diodes connected in parallel. This device exhibits multiple peaks in the I-V characteristic. When a load resistor is connected, the circuit can be operated in a multiple stable mode. With this concept, implementation of three-state and four-state memory cells are made. In the three-state case the operating points at voltages V₀=0.27 V , V₁=0.42 V, and V₂=0.53 V represent the logic levels 0, 1, and 2. Similarly for the four-state memory cell the logic levels voltages are V₀=0.35 V, V₁=0.42 V, V₂=0.54 V, and V ₃=0.59 V. A suggestion of an integrated device structure using this concept is also presented     

Low-power performance of 0.5-μm JFET for low-cost MMIC's inpersonal communications

The low-power microwave performance of an enhancement-mode ion-implanted GaAs JFET is reported. A 0.5-μm×100-μm E-JFET with a threshold voltage of V_th=0.3 V achieved a maximum DC transconductance of g_m=489 mS/mm at V _ds=1.5 V and I_ds=18 mA. Operating at 0.5 mW of power with V_ds=0.5 V and I_ds =1 mA, the best device on a 3-in wafer achieved a noise figure of 0.8 dB with an associated gain of 9.6 dB measured at 4 GHz. Across a 3-in wafer the average noise figure was F_min=1.2 dB and the average associated gain was G_a=9.8 dB for 15 devices measured. These results demonstrate that the E-JFET is an excellent choice for low-power personal communication applications     

Si/a-Si:H heterojunction microwave bipolar transistors with cut-offfrequencies ft above 5 GHz

The fabrication of a silicon heterojunction microwave bipolar transistor with an n⁺ a-Si:H emitter is discussed, and experimental results are given. The device provides a base sheet resistance of 2 kΩ/□ a base width 0.1 μm, a maximum current gain of 21 (V_CE=6 V, I_c=15 mA), and an emitter Gummel number G _E of about 1.4×10¹⁴ Scm^-4. From the measured S parameters, a cutoff frequency f_t of 5.5 GHz and maximum oscillating frequency f_max of 7.5 GHz at V_CE=10 V, I_c=10 mA are obtained     

High-performance standard cell library and modeling technique fordifferential advanced bipolar current tree logic

A high-performance standard cell library for the Tektronix advanced bipolar process GST1 has been developed. The library is targeted for the 250-MIPS (million instructions per second) fast reduced instruction set computer (FRISC) project. The GST1 devices have a minimal emitter size of 0.6 μm×2.4 μm and a maximum f _t of 15.5 GHz. By combining advanced bipolar technology and high-speed differential logic, gate propagation delays of 90 ps can be achieved at a power dissipation of 70 mW. The fastest buffers/inverters have a propagation delay of only 68 ps. A 32-b ALU (arithmetic and logic unit) partitioned into four slices can perform an addition in 3 ns using differential standard cells with improved emitter-follower outputs and fast differential I/O drivers. A modeling technique for high-speed differential current tree logic is introduced. The technique gives accurate timing information and models the transient behavior of current trees     

Current-crowding effect in diagonal MOSFET's

Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I_sub condition (V_g =0.5 V_d). However, in the high-gate-bias region (V_g=V_d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I_sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V_g>V_d), this current-crowding effect in the diagonal transistor can be a serious reliability concern     

Gate-controlled negative differential resistance in drain currentcharacteristics of AlGaAs/InGaAs/GaAs pseudomorphic MODFETs

The observation of negative differential resistance (NDR) and negative transconductance at high drain and gate fields in depletion-mode AlGaAs/InGaAs/GaAs MODFETs with gate lengths L _g ~0.25 μm is discussed. It is shown that under high bias voltage conditions, V_ds>2.5 V and V_gs>0 V, the device drain current characteristic switches from a high current state to a low current state, resulting in reflection gain in the drain circuit of the MODFET. The decrease in the drain current of the device corresponds to a sudden increase in the gate current. It is shown that the device can be operated in two regions: (1) standard MODFET operation for V_gs<0 V resulting in f_max values of >120 GHz, and (2) a NDR region which yields operation as a reflection gain amplifier for V_gs >0 V and V_ds>2.5 V, resulting in 2 dB of reflection gain at 26.5 GHz. The NDR is attributed to the redistribution of charge and voltage in the channel caused by electrons crossing the heterobarrier under high-field conditions. The NDR gain regime, which is controllable by gate and drain voltages, is a new operating mode for MODFETs under high bias conditions     

Ion-implanted GaAs/AlGaAs heterojunction FET's grown by MOCVD

The successful fabrication of an ion-implanted GaAs/AlGaAs heterojunction FET device is discussed. Half-micrometer gate-length FET devices are fabricated by ion implantation into GaAs/AlGa heterostructures grown by metalorganic chemical vapor deposition (MOCVD) on 3-in-diameter GaAs substrates. The FET device exhibits a maximum extrinsic transconductance of 280 mS/mm with reduced transconductance variation over 2 V of gate bias. Excellent microwave performance is achieved with an f_t of 40 GHz, which is comparable to results obtained from 0.25-μm gate GaAs MESFETs. The effects of ion implantation on the heterojunction and corresponding device characteristics are also discussed     

High-speed GaAs multipliers fabricated with a high-yield 0.4-μmprocess

A 0.4-μm GaAs IC fabrication process which demonstrates excellent yields for direct-coupled FET logic circuits of up to 5000 gates for high-speed LSI digital applications is discussed. The refractory self-aligned gate process uses 1-μm stepper lithography. An n⁺/n'/buried-p structure results in superior threshold voltage uniformity for a 0.4-μm gate length, with σV _T as low as 8 mV over 3-in wafers. Simple parallel array multipliers were used for process validation. Die-sort yields for a 16-b×16-b multiplier are typically better than 55%, and as high as 88%. A 5000-gate 20-b×20-b multiplier shows yield as high as 61%, and a Poisson yield model predicts a die-sort yield of 30% for a 10000-gate circuit. Multiplication times of 3.6 ns for the 16-b×16-b and 4.5 ns for the 20-b×20-b multiplier have been measured. The corresponding loaded gate delay and power-delay product are 46 ps/gate and 40 fJ, respectively, at room temperature