Current-Mode High Output Impedance Multifunction Filters Employing Minimum Number of FTFNs

In this study, five current-mode FTFN-based multifunction filters are proposed, which realize the same transfer functions in ideal case. All circuits employ two capacitors and three resistors. For each circuit R-C:C-R transformation increases the number of realization possibilities to ten. The proposed topologies simultaneously realize three basic filtering functions using minimum number of FTFNs and provide high output impedances that enable easy cascading in current mode. Sensitivity analysis of the filters show that they have low passive sensitivities, and of the filters are insensitive to current tracking errors, furthermore of the filters are insensitive to voltage tracking errors of the FTFNs. The proposed circuits do not require component matching condition except for notch and allpass responses and permit independent adjustment of without disturbing . Experimental and simulation results are given to verify the theoretical analyses.     

A CMOS Monolithic Image-Reject Filter

A CMOS inductorless image-reject filter based on active RLC circuitry is discussed and designed with the emphasis on low-noise, low-power, and gigahertz-range circuits. Two -enhancement techniques are utilized to circumvent the low characteristics inherent in the simple feedback circuit. The frequency tuning is almost independent of tuning, facilitating the design of the automatic tuning circuitry. The stability and the tuning scheme of the filter are also discussed. Simulations using 0.6 m CMOS technology demonstrate the feasibility of the tunable image-reject filter for GSM wireless applications. Simulation results show 4.75 dB voltage gain, 9.5 dB noise figure, and –20 dBm IIP3 at a passband centered at 947 MHz. The image signal suppression is 60 dB at 1089 MHz and the power consumption is 27 mW.     

The Design of a 2-V 900-MHz CMOS Bandpass Amplifier

A 900 MHz low-power CMOS bandpassamplifier suitable for the applications of RFfront-end in wireless communication receiversis proposed and analyzed. In this design, thetemperature compensation circuit is used tostabilize the amplifier gain so that theoverall amplifier has a good temperaturestability. Moreover, the compact tunablepositive-feedback circuit is connected to theintegrated spiral inductor to generate thenegative resistance and enhance its value. The simple diode varactor circuit isadopted for center-frequency tuning. These twoimproved circuits can reduce the powerdissipation of the amplifier. An experimentalchip fabricated by 0.5 mdouble-poly-double-metal CMOS technologyoccupies a chip area of ; chip area. The measuredresults have verified the performance of thefabricated CMOS bandpass amplifier. Under a2-V supply voltage, the measured quality factoris tunable between 4.5 and 50 and the tunablefrequency range is between 845 MHz and 915 MHz. At , the measured is 20 dB whereas thenoise figure is 5.2 dB in the passband. Thegain variation is less than 4 dB in the rangeof 0–80^°C. The dc powerdissipation is 35 mW. Suitable amplifier gain,low power dissipation, and good temperaturestability make the proposed bandpass amplifierquite feasible in RF front-endapplications.     

Optimizing CMOS Transconductor-C Filters for Low Power Wide Band Operation

A novel figure of merit to describe the bandwidth power efficiency of CMOS transconductors— is proposed and optimized for cross-coupled differential pair transconductor structures. The optimization is done in two different ways: univariable unconstrained and multivariable constrained. It is revealed that not only dc biases but also ac input phases can affect the bandwidth power efficiency of the transconductor. The bias voltages which can lead to best ratio at different ac phase combinations are obtained and presented in the article. HSPICE simulations are conducted to verify the theoretical predictions. On the basis of the cross-coupled differential pair transconductor, a biquadratic transconductor-C filter configuration is implemented. The frequency vs. power characteristic of the filter is studied for both optimally- and non-optimally-biased transconductor. It is shown that the optimization of the transconductor structure can result in performance improvement of the transconductor-C filter. The deviation of the optimal bias condition between the transconductor alone and the transconductor-C filter due to the inclusion of peripheray circuitries in the filter is discussed in the article.     

A DDS Synthesizer with Digital Time Domain Interpolator

A DDS type circuit structure for producing numericallyprogrammable square wave clock signal is presented. The high speed D/Aconverter needed in conventional DDS systems is replaced by an tap delay line time domain interpolator thateffectively increases the sampling rate by a factor of . Thus the circuit can be used up to full clock rate withoutimage filtering. A prototype IC with clock frequency of 30 MHz, 5 bitinterpolator and SFDR of –40 dBc up to 10 MHz and –33 dBcup to 15 MHz has been designed and tested.     

A Symbolic Circuit Analysis-Oriented Algorithm for Finding a Common Tree of the Current and Voltage Graphs

A fundamental problem of symbolic analysis of electric networks when using the signal-flow (SFG) graph method is to find the common tree of the current and voltage graph ( and , respectively). In this paper we introduce a novel method in order to determine a common tree of both graphs, which may be used to obtain the symbolic network transfer function when carrying out the small-signal analysis of linear(ised) circuits.     

A Small Area Charge Sensitive Readout Chain with a Dual Mode of Operation

A charge sensitive readout chain has been designed and fabricated in acommercially available 0.8 m CMOS technology. The readout chain is optimizedfor pixel detectors measuring soft X-ray energies up to 20 KeV. In the first modean analog signal proportional to input charge is generated and processed in realtime. In the second mode a peak-and-hold operation is enabled and therelevant signal is processed in later time. This dual mode of operation iscontrolled by an external digital signal. The readout chain consists of a chargeamplifier, a shaper, an operational amplifier which can either operate as avoltage amplifier or a peak detector and an output buffer. Its area is . The gain at the shaper output is 378 mv/fC, theENC is 16 rms at 160 nsec shaping time. The overall gainis 557 mV/fC, the ENC is rms with 240 nsec peaking timeand 1.4 sec recovery time. The overall power dissipation is 1.5 mWatt with aload capacitance of 25 pF.     

A Fully Integrated, Low Noise and Low Power BiCMOS Front-end Readout System for Capacitive Detectors

Bipolar transistors are interesting for low noise front-end readout systems when high speed and low power consumption are required. This paper presents a fully integrated, low noise front-end design for the future Large Hadron Collider (LHC) experiments using the radiation hard SOI BiCMOS process. In the present prototype, the input-referred Equivalent Noise Charge (ENC) of 990 electrons (rms) for 12 pF detector capacitance with a shaping time of 25 ns and power consumption of 1.4 mW/channel has been measured. The gain of this front-end is 90 mV/MIP (Minimum Ionisation Particle: 1 fC) with non-linearity of less than 3% and linear input dynamic range is MIP. These results are obtained at room temperature and before irradiation. The measurements after irradiations by high intensity pion beam with an integrated flux of pions/cm² are also presented in this paper.     

Finite-Memory Systems

Let K be a field, k and n positive integers and let matrices with coefficients in K. For any function

Generalization of a Theorem for Replacing CCIIs by CFOAs in Current-Mode Circuits

A current feedback op-amp (CFOA) has the advantage that feedback structures in current-mode circuits are more easily devised because the voltage buffer at the output of the CFOA does not load the output of the integral positive, second-generation current conveyor (CCII⁺) that constitutes part of the CFOA. In this paper, the changes on the current mode transfer function of a linear circuit composed of a subnetwork connected to a CCII⁺ are determined when the CCII⁺ is replaced by a CFOA and a feedback component is connected from the output of the CFOA to an independent node of . Two applications of the results are provided. A new theorem is then presented which generalizes the results. This theorem should be useful for the comparison, synthesis, and improvement of linear current-mode signal processing circuits.     

Planar defects and double-domain epitaxy in epitaxial YSi<Subscript>2−x</Subscript> and ErSi<Subscript>2−x</Subscript> thin films on Si substrates

Interfacial reactions of Y and Er thin films on both (111)Si and (001)Si have been studied by transmission electron microscopy (TEM). Epitaxial rare-earth (RE) silicide films were grown on (111)Si. Planar defects, identified to be stacking faults on planes with 1/6 displacement vectors, were formed as a result of the coalescence of epitaxial silicide islands. Double-domain epitaxy was found to form in RE silicides on (001)Si samples resulting from a large lattice mismatch along one direction and symmetry conditions at the silicide/(001)Si interfaces. The orientation relationships are [0001]RESi_2−x// Si, RESi_2−x//(001)Si and [0001]RESi_2−x/ Si, RESi_2−x//(001)Si. The density of staking faults in (111) samples and the domain size in (001) samples were found to decrease and increase with annealing temperature, respectively.     

BIBO Stability of D-Dimensional Filters

Consider the class of d-dimensional causal filters characterized by a d-variate rational function analytic on the polydisk . The BIBO stability of such filters has been the subject of much research over the past two decades. In this paper we analyze the BIBO stability of such functions and prove necessary and sufficient conditions for BIBO stability of a d-dimensional filter. In particular, we prove if a d-variate filter H(z) analytic on has a Fourier expansion that converges uniformly on the closure of , then H(z) is BIBO stable. This result proves a long standing conjecture set forth by Bose in [3].     

A 5.8 GHz Low Noise Amplifier for Wireless LAN Applications in Silicon Bipolar Technology

A monolithic integrated low-noise amplifier for operation in the 5.8-GHzband is described. Two different versions have been implemented where the biasing wasadapted to allow operation over a different range of supply voltage. At 5-V, theamplifiers gain is about 17-dB, with a noise figure of 4.2-dB and 1-dB compressionpoint at –15-dBm input power. The circuits have been designed utilizing a0.6-micron silicon bipolar production technology, featuring npn transistors with and of about20-GHz.     

A kinetic study of structured surface relief patterning of GaP (\bar 1\bar 1\bar 1)

Orientation dependent etching of photolithographically patterned GaP was investigated using solutions of HCl:CH₃COOH:H₂O₂. The pattern was prepared using standard ultraviolet lithography and was a two-dimensional grid with an 18 μm repeat, consisting of 15 μm squares separated by 3 μm spaces. The mask sides were aligned along the and directions. Under appropriate etching conditions, high quality arrays of pyramids were prepared. These pyramids were defined by , and facets. It was shown that the etching process depended on the degree of solution aging after initial mixing. For a freshly prepared solution, the etching rate showed an inverse dependence on time. For short etching times (below 5 min), an intermediate etching profile was followed, while for long times (greater than 5 min) etching was kinetically controlled. We demonstrated that controlled etching at extremely low rates (0.1–0.5 μm/min) is feasible with this new approach.     

New approach to the analysis of negative magnetostriction in two-dimensional structures

It is shown that the Fourier transform of the negative magnetoresistance associated with the interference correction to the conductivity contains information about the distribution function of the closed trajectories with respect to their areas and about the dependence of the length of the closed trajectories on their area . On the basis of this result a method is proposed for analyzing the negative magnetoresistance. It is used to process experimental results in a twodimensional structure with a doped barrier. It is shown that the function in the investigated structure is largely determined by the scattering anisotropy. Fiz. Tekh. Poluprovodn. 33, 986–989 (August 1999)     

The shape of self-assembled InAs islands grown by molecular beam epitaxy

We have determined the shape of InAs quantum dots using reflection high energy electron diffraction. Our results indicate that self-assembled InAs islands possess a pyramidal shape with {136} bounding facets. This shape is characterized by C_2v symmetry and a parallelogram base, which is elongated along the direction. Cross-sectional transmission electron microscopy images taken along the [110] and directions as well as atomic force microscopy images strongly support the {136} shape. Furthermore, polarization-resolved photoluminescence spectra show strong in-plane anisotropy, with emission predominantly polarized along the direction, consistent with the proposed quantum dot shape.     

On the Scalability of 2-D Discrete Wavelet Transform Algorithms

The ability of a parallel algorithm to make efficient use of increasing computational resources is known as its scalability. In this paper, we develop four parallel algorithms for the 2-dimensional Discrete Wavelet Transform algorithm (2-D DWT), and derive their scalability properties on Mesh and Hypercube interconnection networks. We consider two versions of the 2-D DWT algorithm, known as the Standard (S) and Non-standard (NS) forms, mapped onto P processors under two data partitioning schemes, namely checkerboard (CP) and stripped (SP) partitioning. The two checkerboard partitioned algorithms (Non-standard form, NS-CP), and as (Standard form, S-CP); while on the store-and-forward-routed (SF-routed) Mesh and Hypercube they are scalable as (NS-CP), and as (S-CP), respectively, where M ² is the number of elements in the input matrix, and (0,1) is a parameter relating M to the number of desired octaves J as . On the CT-routed Hypercube, scalability of the NS-form algorithms shows similar behavior as on the CT-routed Mesh. The Standard form algorithm with stripped partitioning (S-SP) is scalable on the CT-routed Hypercube as M ² = (P ²), and it is unscalable on the CT-routed Mesh. Although asymptotically the stripped partitioned algorithm S-SP on the CT-routed Hypercube would appear to be inferior to its checkerboard counterpart S-CP, detailed analysis based on the proportionality constants of the isoefficiency function shows that S-SP is actually more efficient than S-CP over a realistic range of machine and problem sizes. A milder form of this result holds on the CT- and SF-routed Mesh, where S-SP would, asymptotically, appear to be altogether unscalable.     

A Low-Power Block-Matching Cell for Video Compression

This paper describes theimplementation of a block-matching modulewith digital I/O. Algorithmic analysisdemonstrates that the precisionrequirements can be met by a compactcircuit that processes the signal in thecharge domain. The required conversionbetween voltages and charges is achieved byMOS capacitors. As a result, it can befabricated by any inexpensive digital CMOStechnology. A test chip has beenimplemented in a standard CMOS 1.6 mtechnology and the measured energyconsumption is 1.2 nJ per block match usingan pixel matrix. Simulations ofthe same cell in 0.35 m and 0.25 mCMOS technology are presented, showing thescalability of the approach.     

Optimizing Elliptic Filter Selectivity

The problem of determining the band-edge selectivity of elliptic filters and its optimization in filter design is considered. The band-edge selectivity is derived with respect to the -th order elliptic function. The selectivity formula embodies potential trade-offs in filter requirements for improving filter mangitude or delay response. Design examples are submitted in support of the theory. A simple proof describes the Chebyshev filter as an elliptic filter in the limit of infinite stopband corner frequency.     

Identification of prismatic slip bands in 4H SiC boules grown by physical vapor transport

Transmission electron microscopy (TEM) and KOH etching have been used to study the dislocation structure of 4H SiC wafers grown by physical vapor transport. A new type of threading dislocation arrays was observed. Rows of etch pits corresponding to dislocation arrays were observed in vicinity of micropipes, misoriented grains and polytypic inclusions at the periphery of the boules and extended along the directions. Plan view conventional and high resolution TEM showed that the arrays consisted of dislocations threading along the c-axis with Burgers vectors having edge components of the a/3 type. The Burgers vectors were parallel to the corresponding arrays. The dislocation arrays were interpreted as slip bands formed by dislocation glide in the prismatic slip system of hexagonal SiC during post-growth cooling.