A reconfigurable analog processor using coarse-grained,heterogeneous configurable analog blocks for field programmable mixed-signal processing

A field programmable analog array (FPAA), designed for a reconfigurable analog processor, introduces coarse-grained, heterogeneous configurable analog blocks that improves performance and power consumption. Designed in an SMIC standard 0.18 μm CMOS process, mixed-signal processing can be performed by the assistance of an on-chip MCU and configurable digital blocks. Relative precision of the analog processing is 99.5%. A PID controller is shown as an application example. With a total die area of 11 mm², the maximum power consumption is 17.6 mA with a 3.3 V supply voltage, resulting in a 17× improvement in energy-efficiency over current conventional FPAAs.     

一种面向超标量处理器的高能效指令缓存路选择技术

路选择技术可以有效降低指令缓存能耗开销,但已有方法通常会由于预测错误或更新机制复杂而引入额外的取指延迟,导致整体能效性降低.本文面向典型超标量处理器的指令缓存结构,提出了一种高能效的路选择融合技术(Combining Way Selective Cache,CWS-Cache).基于对路预测和路历史技术适用条件的分析,...     

Measuring and Modeling the Power Consumption of Energy-Efficient FPGA Coprocessors for GEMM and FFT

In this paper we analyze the power consumption and energy efficiency of general matrix-matrix multiplication (GEMM) and Fast Fourier Transform (FFT) implemented as streaming applications for an FPGA-based coprocessor card. The power consumption is measured with internal voltage sensors and the power draw is broken down onto the systems components in order to classify the energy consumed by the processor cores, the memory, the I/O links and the FPGA card. We present an abstract model that allows for estimating the power consumption of FPGA accelerators on the system level and validate the model using the measured kernels. The performance and energy consumption is compared against optimized multi-threaded software running on the POWER7 host CPUs. Our experimental results show that the accelerator can improve the energy efficiency by an order of magnitude when the computations can be undertaken in a fixed point format. Using floating point data, the gain in energy-efficiency was measured as up to 30 % for the double precision GEMM accelerator and up to 5 × for a 1k complex FFT.     

Three-dimensional greedy routing in large-scale random wireless sensor networks

In this paper, we investigate how to design greedy routing to achieve sustainable and scalable in a large-scale three-dimensional (3D) sensor network. Several 3D position-based routing protocols were proposed to seek either delivery guarantee or energy-efficiency in 3D wireless networks. However, recent results [1], [2] showed that there is no deterministic localized routing algorithm that guarantees either delivery of packets or energy-efficiency of its routes in 3D networks. In this paper, we focus on design of 3D greedy routing protocols which can guarantee delivery of packets and/or energy-efficiency of their paths with high probability in a randomly deployed 3D sensor network. In particular, we first study the asymptotic critical transmission radius for 3D greedy routing to ensure the packet delivery in large-scale random 3D sensor networks, then propose a refined 3D greedy routing protocol to achieve energy-efficiency of its paths with high probability. We also conduct extensive simulations to confirm our theoretical results.     

Optimal energy-efficiency capacity and sensing tradeoff for hybrid spectrum sharing in CRN

This paper investigates the tradeoff between energy-efficiency capacity and spectrum sensing under hybrid spectrum sharing model,where the spectrum sharing method is based on sensing results of seconda...     

Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise

In this paper, we present an algorithm for computing the bounds on energy-efficiency of digital very large scale integration (VLSI) systems in the presence of deep submicron noise. The proposed algorithm is based on a soft-decision channel model of noisy VLSI systems and employs information-theoretic arguments. Bounds on energy-efficiency are computed for multimodule systems, static gates, dynamic circuits and noise-tolerant dynamic circuits in 0.25-/spl mu/m CMOS technology. As the complexity of the proposed algorithm grows linearly with the size of the system, it is suitable for computing the bounds on energy-efficiency for complex VLSI systems. A key result presented is that noise-tolerant dynamic circuits offer the best trade off between energy-efficiency and noise-immunity when compared to static and domino circuits. Furthermore, employing a 16-bit noise-tolerant Manchester adder in a CDMA receiver, we demonstrate a 31.2%-51.4% energy reduction over conventional systems when operating in the presence of noise. In addition, we compute the lower bounds on energy dissipation for this CDMA receiver and show that these lower bounds are 2.8/spl times/ below the actual energy consumed, and that noise-tolerance reduces the gap between the lower bounds and actual energy dissipation by a factor of 1.9/spl times/.     

Optimizing energy-efficiency for program partitioning and mapping onto multi-core packet processing systems

The sharp increase in bandwidth requirements and versatility of network applications has prompted packet processing systems to widely adopt a multi-core multi-threaded architectural design. A challenging issue when programming such a system is how to fully utilize the processing power in a pipeline-parallel topology. As the power consumption increases, maintaining the energy-efficiency of the whole system also becomes delicate.In this paper, we proposed a strategy based on graph bi-partitioning (Bi-Par) to automatically map the programming code onto the multiple processing cores. The algorithm searches for an optimal configuration of the pipeline depth and the width of each pipeline stage. Steps taken to optimize the performance include iterations over the sub-tasks at the pipeline edges, and performing migration of tasks between cores to improve energy-efficiency. We designed a compiler framework to implement the algorithm, and use an experimental model to validate it. The simulation results show that our approach improves the energy-efficiency in all three benchmarks by between 8.04% and 34%, with a marginal loss in throughput.     

Architecture and Evaluation of an Asynchronous Array of Simple Processors

This paper presents the architecture of an asynchronous array of simple processors (AsAP), and evaluates its key architectural features as well as its performance and energy efficiency. The AsAP processor calculates DSP applications with high energy-efficiency, is capable of high-performance, is easily scalable, and is well-suited to future fabrication technologies. It is composed of a two-dimensional array of simple single-issue programmable processors interconnected by a reconfigurable mesh network. Processors are designed to capture the kernels of many DSP algorithms with very little additional overhead. Each processor contains its own tunable and haltable clock oscillator, and processors operate completely asynchronously with respect to each other in a globally asynchronous locally synchronous (GALS) fashion. A 6×6 AsAP array has been designed and fabricated in a 0.18 μm CMOS technology. Each processor occupies 0.66 mm², is fully functional at a clock rate of 520–540 MHz at 1.8 V, and dissipates an average of 35 mW per processor at 520 MHz under typical conditions while executing applications such as a JPEG encoder core and a complete IEEE 802.11a/g wireless LAN baseband transmitter. Most processors operate at over 600 MHz at 2.0 V. Processors dissipate 2.4 mW at 116 MHz and 0.9 V. A single AsAP processor occupies 4% or less area than a single processing element in other multi-processor chips. Compared to several RISC processors (single issue MIPS and ARM), AsAP achieves performance 27–275 times greater, energy efficiency 96–215 times greater, while using far less area. Compared to the TI C62x high-end DSP processor, AsAP achieves performance 0.8–9.6 times greater, energy efficiency 10–75 times greater, with an area 7–19 times smaller. Compared to ASIC implementations, AsAP achieves performance within a factor of 2–5, energy efficiency within a factor of 3–50, with area within a factor of 2.5–3. These data are for varying numbers of AsAP processors per benchmark.

基于WSN的能量高效MAC协议研究

介质访问控制(medium access control,MAC)协议能效性直接影响着无线传感器网络的寿命.在阐述能量消耗分布及造成无效功耗原因的基础上,分析了MAC协议的性能评价指标和分类方法;重点围绕能量高效,比较研究了当前一些重要的MAC协议,结果表明不存在满足所有要求的协议,仅仅是在各性能间优化折中;最后展望了无线传感器网络MAC协议进一步的研究趋势.     

PVHArray:一种流水可伸缩的层次化可重构密码逻辑阵列结构

针对密码算法的高效能实现问题,该文提出了一种基于数据流的粗粒度可重构密码逻辑阵列结构PVHArray.通过研究密码算法运算及控制结构特征,基于可重构阵列结构设计方法,提出了以流水可伸缩的粗粒度可重构运算单元、层次化互连网络和面向周期级的分布式控制网络为主体的粗粒度可重构密码逻辑阵列结构及其参数化模型.为了提升可重构密码逻辑阵列的算法实现效能,该文结合密码算法映射结果,确定模型参数,构建了规模为4×4的高效能PVHArray结构.基于55nm CMOS工艺进行流片验证,芯片面积为12.25mm²,同时,针对该阵列芯片进行密码算法映射.实验结果表明,该文提出高效能PVHArray结构能够有效支持分组、序列以及杂凑密码算法的映射,在密文分组链接（CBC）模式下,相较于可重构密码逻辑阵列REMUS_LPP结构,其单位面积性能提升了约12.9%,单位功耗性能提升了约13.9%.     

面向异构计算的能效感知调度研究

异构调度可使大规模计算系统采用并行方式聚合广域分布的各种资源以提高性能.传统调度目标追时限约束求高性能而忽视高效能,远不能适应绿色计算科学发展要求.因此,本文在理论上一方面建立融合能效感知的调度模型;另一方面提出适于超计算机混合体系的多学科背景的元启发式优化算法.从技术上解决了面向不同环境目标的调度实施条件界定及调度指标(时间、能耗)实时变化描述等问题.大量仿真实验结果表明:与三个元启发式调度器相比,论文方法在能效及可扩展等方面优势明显;对于高维实例,整体性能改善分别达到8%,15%和17%.     

A new family of CMOS inverter-based OTAs for biomedical and healthcare applications

This paper presents a new family of innovative operational transconductance amplifier (OTA) topologies based on CMOS inverter structures, with improved gain and energy-efficiency. This new family of OTA designs is suitable for biomedical and healthcare circuits and systems, due to the high energy-efficiency, improved gain and low level of noise contribution, when compared to the state-of-the-art in this field. In this paper, two fully-differential implementations are presented, a first one with a double CMOS branch biased by two pairs of voltage-combiners structures in both NMOS and PMOS configurations, and a second one with folded voltage-combiners specifically targeting low voltage applications, e.g., supplies below 1 V. The usage of voltage-combiners to bias the OTAs improves the gain and the gain-bandwidth product, therefore improving the energy-efficiency figure-of-merit. High values of figure-of-merit are achieved in both implementations, i.e., more than 1600 MHz × pF/mA and 2000 MHz × pF/mA, gain values above 53 dB and 50 dB under supply sources of 2 V and 0.7 V respectively. The folded voltage-combiners biased OTA is able to operate correctly under a voltage supply down to 0.7 V with proper DC biasing. The results are finally compared with state-of-the-art in this field and the potential of the circuits is fulfilled using a state-of-the-art layout-aware integrated-circuit optimization framework, AIDA, particularly relevant in order to overcome the device stacking problematic for lower voltages.     

Towards robustness and energy efficiency of cut detection in wireless sensor networks

Reliable, full network connectivity in wireless sensor networks (WSN) is difficult to maintain. Awareness of the state of network connectivity is similarly challenging. Harsh, unattended, low-security environments and resource-constrained nodes exacerbate these problems. An ability to detect connectivity disruptions, also known as cut detection, allows WSN to conserve power and memory while reducing network congestion. We propose ER-CD and LR-CD, protocols that detect cuts while providing energy-efficiency and robustness to attack. Using distributed, cluster-based algorithms, ER-CD recognizes and determines the scope of disrupted connectivity while examining available data for evidence of an attack. For more resource-constrained networks, LR-CD enhances security through the use of a robust outlier detection algorithm. Extensive simulations and a hardware implementation provide experimental validation across a range of network sizes and densities. Results indicate that energy-efficiency can be improved by an order of magnitude in denser networks while malicious nodes are detected at deviations of 1% from expected behavior.     

认知WSN中基于能量有效性自适应观测的梯度投影稀疏重构方法

针对认知无线传感器网络中传感器节点侧的模拟信息转换器对本地感知数据进行稀疏表示与压缩测量,该文提出一种基于能量有效性观测的梯度投影稀疏重构(GPSR)方法。该方法根据事件区域内认知节点对实际感知到的非平稳信号空时相关性结构,映射到小波正交基级联字典进行稀疏变换,通过加权能量子集函数进行自适应观测,以能量有效的方式获取合适的观测值,同时对所选观测向量进行正交化构造测量矩阵。汇聚节点采用GPSR算法进行自适应压缩重构。仿真比较了GPSR自适应重构与正交匹配追踪(OMP)重构算法。仿真结果表明,在压缩比小于0.2的区域内,基于能量有效性观测的GPSR自适应重构效果优于传统随机高斯测量信号重构。在相同节点数情况下,GPSR自适应压缩重构方法在低信噪比区域内具有较小的重构均方误差,且该方法所需观测数明显低于随机高斯观测,同时有效保障了感知节点的能耗均衡。     

协同通信在无线传感网中的应用

差错性能、吞吐量一直是无线通信追求的关键参数,协同通信可以在终端不安装多天线的基础上获得近似MI-MO(Multiple Input Multiple Output)技术的协同分集增益,提高系统性能或吞吐量。能效性是无线传感网中的关键参数,将协同通信应用在基于分簇的无线传感器网络(WSN)中,可以提高整个网络的能效性,以达到节省能量、延长整个网络寿命的目标。介绍了协同通信在无线传感器网络的结合应用方案,对这种结合的能效性能的最新研究给出了分析介绍,最后总结了研究的关键问题以及未来的发展趋势和研究方向。     

Instruction Fetch Energy Reduction with Biased SRAMs

Especially in programmable processors, energy consumption of integrated memories can become a limiting design factor due to thermal dissipation power constraints and limited battery capacity. Consequently, contemporary improvement efforts on memory technologies are focusing more on the energy-efficiency aspects, which has resulted in biased CMOS SRAM cells that increase energy efficiency by favoring one logical value over another. In this paper, xor-masking, a method for exploiting such contemporary low power SRAM memories is proposed to improve the energy-efficiency of instruction fetching. Xor-masking utilizes static program analysis statistics to produce optimal encoding masks to reduce the occurrence of the more energy consuming instruction bit values in the fetched instructions. The method is evaluated on LatticeMico32, a small RISC core popular in ultra low power designs, and on a wide instruction word high performance low power DSP. Compared to the previous “bus invert” technique typically used with similar SRAMs, the proposed method reduces instruction read energy consumption of the LatticeMico32 by up to 13% and 38% on the DSP core.     

Energy-efficient MAC in ad-hoc networks inspired by conflict resolution concepts

In this paper, we address the medium access control (MAC) problem in ad-hoc networks from the energy-efficiency perspective and develop a residual-energy-based collision resolution algorithm (CRA) for energy-limited terminals. In this interval-splitting-based algorithm, packets involved in a collision are partitioned into subsets according to the amount of residual battery energy left at the corresponding terminals, and retransmissions are scheduled according to a tree structure. To avoid possible performance degradations for cases of not evenly spread battery energies, we propose a hybrid approach that interchangeably uses energy-based and first-come-first-served CRA’s to resolve packet conflicts. We extend the proposed energy-based collision resolution (CR) approach to cases without hard energy constraints but, rather, with energy-efficiency objectives. The algorithm then utilizes the distance from the receiver as the criterion. We then address energy-efficient conflict resolution in general multi-hop ad-hoc networks. In this context, a useful but yet simple method is proposed to reduce the interdependence between collision resolution processes at different receivers, which would otherwise distort the general structure of tree-splitting algorithms. We evaluate the proposed algorithms via simulation for communication systems ranging from simple single-cell classical collision channel models to general multi-hop wireless ad-hoc networks.     

A survey of transport protocols for wireless sensor networks

In this article we present a survey of transport protocols for wireless sensor networks (WSNs). We first highlight several unique aspects of WSNs, and describe the basic design criteria and challenges of transport protocols, including energy-efficiency, quality of service, reliability, and congestion control. We then provide a summary and comparison of existing transport protocols for WSNs. Finally, we discuss several open research problems.     

服务器能效测试新方法(上)

服务器指的是管理资源并为用户提供服务的计算机,相对于普通PC来说,服务器在稳定性、安全性、性能等方面都要求更高,因此CPU、芯片组、内存、磁盘系统、网络等硬件和普通PC有所不同。服务器的应用范围涉及政府、教育、医疗、企业等部门,从个人PC到工作站,再到大型超级计算机,是互联网产业不可缺少的一个部分,服务器发挥着重要作用。其在数据中心及云存储中的运用尤为重要。因此,在"绿色"、"低碳"成为ICT产业发展主要趋势的今天,如何评价服务器的节能指标,以及如何提高服务器的能源利用率,成为人们关注的重点。     

ACM: An Energy-Efficient Accuracy Configurable Multiplier for Error-Resilient Applications

The multimedia applications such as image, audio and video processing allow approximation in computations, provided that, errors are of definite types and have austerities within confined limits, thus exhibiting error-resiliency. An approximate arithmetic circuit can be exploited to avail this error-resiliency for improving energy-efficiency. This paper presents an approximate multiplier that provides higher energy-efficiency at the cost of minor loss of accuracy. The proposed multiplier offers twofold improved performance because of reduced level of gates and curtailed inherent switched capacitances. Further, to achieve variable accuracy, an Accuracy Configurable Multiplier (ACM) algorithm is proposed that provides improved Speed-Power-Area-Accuracy (SPAA) metrics. The proposed ACM enables dynamic accuracy configurability via small error correction logic. Simulation results over accurate 8-bit multiplier indicate 57.37% and 25.17% reduced power and area, respectively. Moreover, accuracy configurability is achieved with only 10.5% and 12.32%, area and power overhead, respectively. Moreover, the proposed multiplier in real applications such as Gaussian smoothing filter attains better SPAA tradeoff over the existing approximate multipliers.