Real-time morphology processing using highly parallel 2-D cellular automata CAM/sup 2/

Mathematical morphology is a promising computer paradigm based on set theory and has many applications in image processing. Although some architectures have been proposed, there are as yet no compact, practical computers that can handle a variety of morphological operations with large, complex structuring elements at video rates. This has prevented the great potential of morphology from being fully realized. This paper describes a morphology processing method that uses a highly parallel two-dimensional (2-D) cellular automaton architecture called it CAM/sup 2/ (Cellular AutoMata on Content Addressable Memory). New mapping methods achieve high-throughput complex morphology processing. Evaluation results show that CAM/sup 2/ performs one morphological operation for basic structuring elements within 30 /spl mu/s. Furthermore, CAM/sup 2/ can also handle an extremely large and complex structuring element of 100/spl times/100 at video rates. CAM2 will increase the potential use of morphology and make a significant contribution to the development of various real-time image processing systems.     

基于模糊聚类的视频对象分割

提出了一种基于模糊聚类的视频对象分割方法.首先通过对连续三帧视频图像进行二次差分来得到二次差分图像;然后估计噪声的特征参数滤除背景噪声,提取出视频对象的运动区域;再利用改进的FCM聚类算法对二次帧差图像中的视频对象运动区域进行空域分割,对空域分割结果进行形态学处理,得到视频对象掩模;最终获得较为理想的视频对象.实验结果表明,该算法能够较为准确地分割出视频对象,并且在空间准确度上占优.     

A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications

A MIMD based multiprocessor architecture for real-time video processing applications consisting of identical bus connected processing elements has been developed. Each processing element contains a RISC processor for controlling and data-dependent tasks and a Low Level Coprocessor for fast processing of convolution-type video processing tasks. To achieve efficient parallel processing of video input signals, the architecture supports independent processing of overlapping image segments. Running at a clock rate of 40 MHz, a single processing element provides a peak performance of 640 Mega arithmetic operations per second (MOPS). For the real-time processing of basic video processing tasks like 3×3 FIR-filter, 8×8 2D-DCT and motion estimation, a single processing element provides a sufficient computational rate for video signals with Common Intermediate Format (CIF) at a frame rate up to 30 Hz. For hybrid source coding of CIF video signals at a frame rate of 30 Hz a multiprocessor system consisting of six processing elements is required. A linear speedup of the multiprocessor system compared to a single processing element is achieved. A VLSI implementation of a processing element in 0.8 µm CMOS technology is under development.     

Global feature extraction operations for near-sensor imageprocessing

Near-sensor image processing (NSIP) is a new approach to low-level image processing in which the ability to perform global operations is crucial. We define a 2-D global logic unit (GLU), which consists of simple logical circuits arranged in a regular net, and describe how to perform powerful segmentation and feature-extracting operations using this net. Typical segmentation operations performed by the net are hole filling, smallest circumscribing rectangle, thresholding with hysteresis, and arbitrary propagation patterns. We describe how to obtain features like the position of an object in the image. Finally, we show that the NSIP concept, including the global functions, can be implemented in a single chip using today's VLSI technology.     

一种基于定时段区域补偿的视频对象分割算法

在传统时空联合算法的基础上,提出了一种基于定时段区域补偿的视频对象分割后处理算法。首先,通过对帧差图像进行噪声抑制和膨胀连接获得变化检测模板;然后,对原始图像进行开闭重构简化,求取形态学梯度,通过对形态学梯度图像进行非线性变换和梯度等级划分并最终由分水岭算法获得对象的精确边界,通过比例运算提取出视频对象的初始二值化模板;最后,通过定时段区域补偿获得最终的完整视频对象模板。实验结果证明了该算法的正确性和有效性。     

基于面积约束和自适应梯度修正的分水岭图像分割

图像中的噪声或非规则细节干扰易导致形态学 分水岭产生较严重的过分割,为了在消除过分割的同时尽可能 保持图像目标边界的准确定位,提出了一种基于面积约束和自适应梯度修正的分水岭图像分 割方法。首先对图像进行梯 度变换,采用区域面积约束滤除狭小高梯度尖峰对应的噪声和非规则细节;然后建立梯度级 与结构元素大小之间的函数 关系,并以相对应的结构元素对梯度图像进行粘性形态学(VM)闭运算,消除低梯度噪声及非 规则细节,实现梯度图像的自适 应修正,由于VM闭运算对梯度图像进行修正时,对目标仅作轻度或不作修正,因 而能够最大限度的保持目标轮 廓的准确定位,而对噪声和非规则细节则采用较大尺寸的结构元素进行较大幅度修正,从而 消除产生过分割的因素;最 后对修正图像进行分水岭分割。实验结果表明,本文方法能够在消除过分割的同时,保持目 标轮廓的准确定位。     

A Programmable SIMD Vision Chip for Real-Time Vision Applications

A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 times 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 times 16 PE array is fabricated by the 0.18 standard CMOS process. It has a pixel size of 30 mum times 40 mum and 8.72 mum W power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.     

基于FPGA的微光视频采集与预处理系统设计

针对当前微光视频图像采集与处理系统中数据处理量与系统实时性之间的矛盾,设计了一种基于现场可编程门阵列(Field Programmable Gate Array, FPGA)的实时信号采集与预处理系统。该系统以高性能Xilinx A7系列芯片为主控芯片,使用两片第二代双倍数据率同步动态随机存取存储器(Double-Data-Rate Two Synchronous Dynamic Random Access Memory, DDR2 SDRAM)作为核心存储器件,并定制超感光互补金属氧化物半导体(Complementary Metal Oxide Semiconductor, CMOS)传感镜头作为视频图像采集器件。完成系统的硬件设计之后,通过Xilinx Vivado平台以及Matlab进行软件系统的工程设计与仿真分析,实现了微光环境下视频图像的采集、存储、处理与显示的全过程。实验结果表明,该系统采集的微光视频图像实时性好、动态画面流畅。     

Video object segmentation in rainy situations based on difference scheme with object structure and color analysis

A scheme based on a difference scheme using object structures and color analysis is proposed for video object segmentation in rainy situations. Since shadows and color reflections on the wet ground pose problems for conventional video object segmentation, the proposed method combines the background construction-based video object segmentation and the foreground extraction-based video object segmentation where pixels in both the foreground and background from a video sequence are separated using histogram-based change detection from which the background can be constructed and detection of the initial moving object masks based on a frame difference mask and a background subtraction mask can be further used to obtain coarse object regions. Shadow regions and color-reflection regions on the wet ground are removed from the initial moving object masks via a diamond window mask and color analysis of the moving object. Finally, the boundary of the moving object is refined using connected component labeling and morphological operations. Experimental results show that the proposed method performs well for video object segmentation in rainy situations.     

一种面向对象的视频分割算法

该文讨论面向对象编码的视频分割算法。由于数学形态学工具能够很好地处理诸如大小、形状、对比度和连通性等对图像分割非常重要的特征,这种技术常用来对图像进行帧内分割,得到一些具有某种相似性的区域。然后利用运动信息进行区域合并。为了实现区域合并,该文提出一种新方法来判定局部运动。设计了一个分割细化步骤,对区域边界点进行再判决,可以得到更好的结果。实验结果表明,该文提出的方法对于平稳背景和运动背景中的视频对象分割都是有效的。     

Image segmentation via adaptive K-mean clustering andknowledge-based morphological operations with biomedical applications

Image segmentation remains one of the major challenges in image analysis. In medical applications, skilled operators are usually employed to extract the desired regions that may be anatomically separate but statistically indistinguishable. Such manual processing is subject to operator errors and biases, is extremely time consuming, and has poor reproducibility. We propose a robust algorithm for the segmentation of three-dimensional (3-D) image data based on a novel combination of adaptive K-mean clustering and knowledge-based morphological operations. The proposed adaptive K-mean clustering algorithm is capable of segmenting the regions of smoothly varying intensity distributions. Spatial constraints are incorporated in the clustering algorithm through the modeling of the regions by Gibbs random fields. Knowledge-based morphological operations are then applied to the segmented regions to identify the desired regions according to the a priori anatomical knowledge of the region-of-interest. This proposed technique has been successfully applied to a sequence of cardiac CT volumetric images to generate the volumes of left ventricle chambers at 16 consecutive temporal frames. Our final segmentation results compare favorably with the results obtained using manual outlining. Extensions of this approach to other applications can be readily made when a priori knowledge of a given object is available.     

An Embedded Real-Time Surveillance System: Implementation and Evaluation

This paper presents the design of an embedded automated digital video surveillance system with real-time performance. Hardware accelerators for video segmentation, morphological operations, labeling and feature extraction are required to achieve the real-time performance while tracking will be handled in software in an embedded processor. By implementing a complete embedded system, bottlenecks in computational complexity and memory requirements can be identified and addressed. Accordingly, a memory reduction scheme for the video segmentation unit, reducing bandwidth with more than 70%, and a low complexity morphology architecture that only requires memory proportional to the input image width, have been developed. On a system level, it is shown that a labeling unit based on a contour tracing technique does not require unique labels, resulting in more than 50% memory reduction. The hardware accelerators provide the tracking software with image objects properties, i.e. features, thereby decoupling the tracking algorithm from the image stream. A prototype of the embedded system is running in real-time, 25 fps, on a field programmable gate array development board. Furthermore, the system scalability for higher image resolution is evaluated.     

基于自适应像素分割算法的FPGA设计与实现

为了解决运动目标前景检测的精度问题,提出了一种基于FPGA实现的自适应像素分割系统。该系统通过构建新的背景模型和前景分割检测技术优化检测结果,并对传统的自适应像素分割算法进行了调整和修改,以便在FPGA平台上进行硬件实现。在Xilinx virtex7 FPGA芯片上已完成了硬件测试。试验测试结果显示相比其他算法,本文提出设计的各项性能指标均表现良好,检测精度达到71.4%,平均功耗为6.452 W。能够实现以50 frame/s,实时处理分辨率为720×576的视频流。     

A fast Discrete Wavelet Transform algorithm for visual processing applications

For visual processing applications, the two-dimensional (2-D) Discrete Wavelet Transform (DWT) can be used to decompose an image into four-subband images. However, when a single band is required for a specific application, the four-band decomposition demands a huge complexity and transpose time. This work presents a fast algorithm, namely 2-D Symmetric Mask-based Discrete Wavelet Transform (SMDWT), to address some critical issues of the 2-D DWT. Unlike the traditional DWT involving dependent decompositions, the SMDWT itself is subband processing independent, which can significantly reduce complexity. Moreover, DWT cannot directly obtain target subbands as mentioned, which leads to an extra wasting in transpose memory, critical path, and operation time. These problems can be fully improved with the proposed SMDWT. Nowadays, many applications employ DWT as the core transformation approach, the problems indicated above have motivated researchers to develop lower complexity schemes for DWT. The proposed SMDWT has been proved as a highly efficient and independent processing to yield target subbands, which can be applied to real-time visual applications, such as moving object detection and tracking, texture segmentation, image/video compression, and any possible DWT-based applications.     

基于FPGA的水平集图像分割算法加速器

水平集算法因其出色的性能,在图像分割领域中得到了广泛的应用.同时,与基于深度学习的图像分割算法相比,水平集算法不需要训练数据,大幅降低了数据标记带来的工作量.然而,目前水平集算法主要是基于软件开发,涉及大量复杂的计算,以及计算的多次迭代,导致较高的处理延时与功耗.为了加快水平集算法的处理速度和降低功耗,该文提出了一种基...     

A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine

A network-on-chip (NoC) based parallel processor is presented for bio-inspired real-time object recognition with visual attention algorithm. It contains an ARM10-compatible 32-bit main processor, 8 single-instruction multiple-data (SIMD) clusters with 8 processing elements in each cluster, a cellular neural network based visual attention engine (VAE), a matching accelerator, and a DMA-like external interface. The VAE with 2-D shift register array finds salient objects on the entire image rapidly. Then, the parallel processor performs further detailed image processing within only the pre-selected attention regions. The low-latency NoC employs dual channel, adaptive switching and packet-based power management, providing 76.8 GB/s aggregated bandwidth. The 36 mm² chip contains 1.9 M gates and 226 kB SRAM in a 0.13 mum 8-metal CMOS technology. The fabricated chip achieves a peak performance of 125 GOPS and 22 frames/sec object recognition while dissipating 583 mW at 1.2 V.     

Image segmentation on a 2D array by a directed split and mergeprocedure

A 2D array implementation of image segmentation by a directed split and merge procedure is proposed. Parallelism is realized on two levels: one within the split and merge operations, where more than one merge (or split) may proceed concurrently, and the second between the split and merge operations, where several splits may be performed in parallel with merges. Both the split and merge operations are based on nearest neighbor communications between the processing elements (PEs), and facilitating low communication costs. The basic arithmetic operations required to perform split and merge are comparison and addition, allowing a simple structure of the PE as well as a hardwired control. A local of 512 bytes is sufficient to hold the interim data associated with each PE. A prototype PE has been constructed using 3 μm double-metal CMOS technology. Scaling up to 0.8 μm, it is possible to incorporate 32 PEs on a 5 cm² chip. With sufficiently large PE window sizes, image segmentation can be achieved in linear time     

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 μm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems. Shao-Yi Chien was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University (NTU), Taipei, in 1999 and 2003, respectively. During 2003 to 2004, he was a research staff in Quanta Research Institute, Tao Yuan Shien, Taiwan. In 2004, he joined the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, as an Assistant Professor. His research interests include video segmentation algorithm, intelligent video coding technology, image processing, computer graphics, and associated VLSI architectures. Bing-Yu Hsieh was born in Taichung, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and Ph. D. degree in the Graduate Institute of Electronics Engineering from National Taiwan University (NTU), Taipei, in 2000 and 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Shyh-Yih Ma received the B.S.E.E, M.S.E.E, and Ph.D. degrees from National Taiwan University in 1992, 1994, and 2001, respectively. He joined Vivotek, Inc., Taipei County, in 2000, where he developed multimedia communication systems on DSPs. His research interests include video processing algorithm design, algorithm optimization for DSP architecture, and embedded system design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the BS, MS, and Ph.D degrees in Electrical Engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. At 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is Professor of National Taiwan University. From 2004, he is also the Executive Vice President and the General Director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding system. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tan Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He is also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He serves as Associate Editor of IEEE Trans. on Circuits and Systems for Video Technology from June 1996 until now and the Associate Editor of IEEE Trans. on VLSI Systems from January 1999 until now. He was the Associate Editor of the Journal of Circuits, Systems, and Signal Processing from 1999 until now. He served as the Guest Editor of The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, November 2001. He is also the Associate Editor of the IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. From 2002, he is also the Associate Editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Award from ROC Computer Society in 1990 and 1994. From 1991 to 1999, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Out-standing Research Award from NSC, and the Dragon Excellence Award for Acer. He is elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

Implementation of a bipolar real-time image signal processor-RISP-II

The high-speed digital image signal processor RISP-II, an improved version of the original real-time image signal processor (RISP) for gray-level image processing, is discussed. RISP-II has a microprogrammable architecture and a per-chip processing speed of 100 million instructions per second. Multichip processing has been realized by two added features: parallelism and pipelining. In the multichip mode its processing power can easily be increased. As a result, RISP-II is capable of real-time processing of the image data of a moving object. RISP-II, implemented in an advanced bipolar ECL technology, has integrated 20600 elements on a chip of 6/spl times/6 mm/SUP 2/. Its power dissipation is 1.6 W.     

DSP图像处理技术在板带纠偏系统中的应用

运用DSP图像处理的解决办法,设计了一套基于DSP数字图像处理技术的板带纠偏电视检测可视化系统.DSP计算速度快、可并行处理,成功解决了视频检测数据处理量大、系统实时性要求高之间的矛盾.设计中所选取的TMS320DM642芯片作为一款专用的数字多媒体处理芯片,具有丰富的外围接口和特色的视频图像采集功能,这就使该图像处理模块集成了图像的采集回放与图像处理的功能,摒弃了单独的图像采集卡,避免了数据传输过程中所出现的问题.在深入研究DSP系统的基础上,制定了系统实现的方法并在实验室条件下实现了板带纠偏与视频检测,检验结果完全能够满足实时性和精度要求.