Submicrometer Silicon MOSFET's fabricated using focused ion-beam lithography

Submicrometer n-channel enhancement-mode silicon MOSFET's with polysilicon gate lengths as small as 0.35 µm were fabricated using focused-ion-beam lithography. The polysilicon gate was patterned by a 80-kV Au-Si ion beam using a negative polystyrene resist. Transconductance values of 140 mS/mm were obtained for devices with gatelengths of 0.4 µm and gate oxide thickness of 10 nm. Short-channel effects were minimal in these devices.     

0.15 µm Channel-length MOSFET's fabricated using e-beam lithography

We have fabricated MOSFET's with channel lengths as short as 0.1 µm by a modified NMOS process. The devices have been designed according to parameters obtained from numerical simulation. Electron-beam lithography has been used to define patterns at all levels with the negative resist GMC in a tri-level configuration. Heat treatments have been as short as possible to preserve very shallow source-drain junction depths (<0.1µm). We observe quasi-long channel behavior for low bias voltages. Measured values for the transconductance are among the highest ever reported. For a channel lengthL = 0.14µm, we obtaing_{m} = 180mS/mm for a gate oxide thickness of 160Å.     

Mobility degradation in very thin Oxide p-channel MOSFET's

The effective hole mobility in large-area p-channel MOSFET's decreases systematically over a wide range of oxide fields as the gate oxide thickness decreases from 240 to 31 Å. A scattering mechanism based on the variations of the gate-charge-induced Coulomb scattering potential in the channel resulting from gate oxide thickness and/or structural fluctuations over the gate area is proposed to explain the results.     

Accurate nano-EB lithography for 40-nm gate MOSFETs

Nanometer electron beam lithography has been used for fabrication of sub-0.1 μm MOSFETs. Chemically amplified resist as a single layer mask showed high resolution by optimizing the resist process. Proximity effect correction was applied and showed a good line width control. Operation of a 40nm-polysilicon gate NMOSFET was confirmed.     

Hot-electron-induced instability in 0.5-μm p-channel MOSFETspatterned using synchrotron X-ray lithography

Radiation damage caused by X-ray includes positive oxide charge, neutral traps, and interface states. Although several annealing steps are performed throughout the entire fabrication process, the radiation damage, particularly neutral traps, is not completely annealed out. The hot-electron-induced instability in p-channel MOSFETs is significantly increased due to the enhanced electron trapping in the oxide by residual traps. However, the degradation in n-channel MOSFETs due to channel-hot carriers is not significantly increased by X-ray lithography since n-channel MOSFETs are susceptible to interface state generation by hot carriers but are relatively insensitive to the degradation due to electron trapping. The results suggest that p-channel MOSFETs in addition to n-channel MOSFETs need to be carefully examined for hot carrier-induced instability in CMOS VLSI circuits patterned using X-ray lithography and/or when the radiation damage is incurred in the back-end-of-the-line processing     

Sub-0.1 μm NMOS transistors fabricated using laser-plasmapoint-source X-ray lithography

We report the experimental results of the first MOSFET's ever fabricated using a laser plasma-source X-ray stepper. The minimum gate length of these transistors is 0.12 μm with an effective channel length of 0.075 μm. These transistors were patterned using a mix-and-match lithography scheme where the gate level was printed using a 1.4 nm plasma-source X-ray stepper while the other layers were patterned using optical lithography     

Study of RF transistor with submicron T-shaped gate fabricated by nanoimprint lithography

The results devoted to the development of a method for creating an RF transistor, in which a T-shaped gate is formed by nanoimprint lithography, are presented. The characteristics of GaAs p-HEMT transistors have been studied. The developed transistor has a gate “foot” length of the order of 250 nm and a maximum transconductance of more than 350 mS/mm. The maximum frequency of current amplification f _t is 40 GHz at the drain-source voltage V _DS = 1.4 V and the maximum frequency of the power gain f _max is 50 GHz at V _DS = 3 V.     

Blazed diffraction gratings fabricated using X-ray lithography: fabrication, modeling and simulation

Diffraction gratings are used in optical communications devices, spectrographs, optical scanners, monochromators, and in other instances. Diffraction gratings are either transmission or reflection. Reflective gratings are, usually, either ruled or holographic. Blazed gratings (step-echelette or phase gratings) are non-planar gratings. We present the fabrication of blazed diffraction gratings using X-ray lithography. We model, theoretically, the development process of X-ray exposed X-ray sensitive resist material (polymethyl methacrylate), and we establish a simulation algorithm, the ray-tracing algorithm based on the Hamilton–Jacobi equation. Theoretical predictions based on simulation results validate fully the fabricational results.     

25-nm p-channel vertical MOSFETs with SiGeC source-drains

The scaling of vertical p-channel MOSFETs with the source and drain doped with boron during low temperature epitaxy is limited by the diffusion of boron during subsequent side wall gate oxidation. By introducing thin SiGeC layers in the source and drain regions, this diffusion has been suppressed, enabling for the first time the scaling of vertical p-channel MOSFETs to under 100 nm in channel length to be realized. Device operation with a channel length down to 25 nm has been achieved     

Sub-quarter-micrometer gate-length p-channel MOSFETs with shallowboron counter-doped layer fabricated using channel preamorphization

A technique for forming shallow boron-doped layers for channel doping using preamorphization (channel preamorphization) is described. An extremely shallow boron-doped layer for shallow channel doping has been formed using preamorphization and rapid thermal annealing. Boron peak concentration around the surface is 3.5×10¹⁸ cm ^-3, and the depth at which the boron concentration becomes 10 ¹⁷ cm^-3 is 450 Å. In contrast, the depth is as large as 900 Å for nonpreamorphized samples. It is found that the shallow boron-doped layer formation is made possible because enhanced diffusion arising from ion implantation damage as well as the channeling in boron ion implantation is suppressed by preamorphization. It is also found that preamorphization does not affect MOS capacitor characteristics so long as the amorphous/crystalline interface is sufficiently deep, which allows that channel preamorphization is readily applicable to channel doping in MOSFET fabrication. To substantiate the experimental results, buried-channel p-MOSFETs with a shallow boron counterdoped layer using channel preamorphization have been successfully fabricated. Channel preamorphization did not degrade carrier mobility and improved MOSFET characteristics in the sub-quarter-micrometer-gate-length region suppressing short-channel effects due to the shallower counterdoped boron profile. High-performance 0.2-μm-gate-length p-MOSFETs with good subthreshold characteristics have been fabricated     

100-nm n-/p-channel I-MOS using a novel self-aligned structure

We have fabricated a 100-nm n-/p-channel I-MOS by adopting a novel structure. The proposed structure shows some advantages over the conventional one in terms of self-alignment and reduced number of photolithography masks. It leads to low fabrication cost, accelerated scaling down, and enhanced performance due to reduced parasitic elements. It shows a normal transistor operation with small subthreshold swing less than 11.8 mV/dec at room temperature. The n- and p-channel I-MOS have an ON/OFF current of 81.1/2.8 and 78.2/3.4 /spl mu/A per /spl mu/m, respectively. The device performance provides a promise for near-ideal switch application.     

Direct observation of the gate Oxide electric field distribution in Silicon MOSFET's

The charge collected within the SiO2layer of an MOS capacitor during bombardment with kilovolt electrons is approximately proportional to the field in the oxide. We have used this proportionality to form SEM images of the field distribution in MOSFET channels.     

Theoretical analysis on threshold characteristics of surface-channel MOSFET's fabricated on a buried Oxide

Simple models for threshold characteristics of surface-channel MOSFET's, which are fabricated on a buried oxide covered by an electric field shielding layer, are proposed. The electric field shielding effect is taken into account when the Poisson's equation is solved. Threshold voltage expressions are derived from the solution of the Poisson's equation and the surface-channel charge neutrality relationship. Theoretical analysis shows that the thinner silicon layer leads to enhancement of the electric field which results in the reduction of the short-channel effect.     

Electrical characteristics of MOSFET's utilizing Oxygen—Argon sputter-deposited gate Oxide films

This paper presents a detailed look at the electrical characteristics of MOSFET's utilizing oxygen-argon sputter-deposited gate-oxide films for low-temperature MOSFET fabrication. The gate-oxide films are deposited at low temperature (200°C) by oxygen-argon sputtering of an SiO2target. The MOSFET's so formed are confirmed to have triode characteristics. Moreover, oxygen mixing makes it possible to considerably improve the MOSFET field-effect mobility and subthreshold slope over those of argon-only sputter-deposited film to 700 cm²/V's and 170 mV/decade. These improvements are found to be caused by the remarkable reduction in surface-state density. These results confirm the usefulness of oxygen-argon sputter-deposited gate-oxide films for MOSFET fabrication at low temperature.     

Submicron gate MOSFET's with channel-doped separate gate structures (SG-MOSFET's)

Submicron gate MOSFET's with a new device structure are presented. The device features gate separation between the source and gate and between the gate and drain. The minimum gate length limited by VTHlowering is extended into the submicron range. Experimental results showed pentode-like current-voltage characteristics without punchthtough, even in the submicron range. Experimental results of inverter circuits and theoretical analysis predict high-speed operation in the subnanosecond region.     

Submicron T-shaped gate HEMT fabrication using deep-UV lithography

A new combination of low/high/low sensitivity tri-layer (PMMA/PMIPK/PMMA) resist system was used for deep UV lithography to-fabricate submicron T-shaped gate. Gate length as narrow as 0.2 μm is achieved. GaAs HEMTs with 0.3 μm T-shaped Ti/Pt/Au gate are fabricated using this technology. The HEMT demonstrated a 0.6 dB noise figure and 13 dB associated gain at 10 GHz. This deep UV lithography process provides a high throughput and low cost alternative to E-beam lithography for submicron T-gate fabrication     

Sub-60-nm quasi-planar FinFETs fabricated using a simplifiedprocess

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 μA/μm (or 1 mA/μm, depending on the definition of the width of the double-gate device) for V_g-V _t=V_d=1 V. The electrical gate oxide thickness in these devices is 21 Å, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness     

Fabrication of submicron photon sieve using E-beam lithography and X-ray lithography

In this paper, a new hybrid method to fabricate submicron photon sieve is proposed, where the E-beam lithography and the X-ray lithography are used. It is found that 2.8 μm thickness of the polyimide film, 400 nm thickness of the ZEP-520 and 280 μC/cm² exposure dose are good for E-beam lithography, while 500 nm thickness of the PMMA and 30 s developing time are good for X-ray lithography. We have successfully fabricated the photon sieve with these parameters (the diameter of photon sieve: 250 μm, the focal length: 150 μm, the diameter of the outmost pinhole: 420 nm). Some key techniques of this method are analyzed respectively, and the error analysis are done at the end of this paper. It provides a direction of nanoscale optical element fabrication with higher resolution and lower cost.     

SiGe-collector trench gate insulated gate bipolar transistor fabricated using multiple target sputtering

A new type of trench gate IGBT (insulated gate bipolar transistor) which uses a SiGe layer for the collector is experimentally investigated. SiGe collectors with different Ge content are deposited by multiple cathode sputtering making low temperature processing possible. The change in turn-off characteristics with Ge content is also investigated. Results indicate that the use of a SiGe collector reduces the tail current at turn-off due to the reduced injection of holes to the n⁻ drift region.     

MOSFET's fabricated in laser-recrystallized Silicon on Quartz using selectively absorbing dielectrical layers

MOSFET's were fabricated in laser-recrystallized silicon islands on fused quartz substrates using a standard n-channel self-registered poly-gate process. Selective absorption obtained with patterned dielectric films was used to control the shape of the melt front during recrystallization of patterned LPCVD polysilicon islands. IR imaging of the laser-heated region was used to optimize and monitor the melt front shape. Devices with various channel lengths and widths were fabricated and the dependence of threshold voltage, channel mobility, and subthreshold leakage on recrystallization conditions and device dimensions were studied. Devices with and without back-channel implants were compared on the same wafer and for the same laser annealing conditions. The back-channel implant consistently reduced the subthreshold leakage to less than 1 pA/µm.