Design criteria of high-Voltage lateral RESURF JFETs on 4H-SiC

Integrated power electronics on SiC have great potential in future power electronics applications. In this paper, a novel vertical channel lateral junction field-effect transistor structure with reduced surface electric field effect is proposed for the first time on 4 H-SiC to address existing challenges in lateral power devices on SiC. Based on an experimentally proven channel design, the detailed design procedure of such a device has been investigated. Design criteria to optimize device forward blocking as well as conduction characteristics are studied. Parameter tolerance and design windows are discussed considering practical issues in device fabrication. Designs that will lead to an optimized tradeoff between device breakdown voltage and specific on-resistance are shown. With an 8-/spl mu/m-long drift region, a 1535-V breakdown voltage and 3.24 m/spl Omega//spl middot/cm/sup 2/ specific on-resistance can be achieved. This represents a figure-of-merit of 737 MW/cm/sup 2/, about 100 times higher than that of the best normally off lateral power devices reported in the literature. The proposed device can be an attractive candidate for power integrated circuit on SiC.     

Trap characterization in buried-gate n-channel 6H-SiC JFETs

We present a detailed characterization of deep traps present in buried gate, n-channel 6H-SiC JFETs, based on transconductance measurements as a function of frequency. Four different deep levels have been identified, which are characterized by activation energies of 0.16, 0.18, 0.28, and 0.54 eV. Furthermore, based on the transconductance frequency dispersion features (upward or downward dispersion), we have been able to infer that three deep levels (0.16, 0.18 and 0.54 eV) are hole traps localized in the p-gate layer and one (0.28 eV) is an electron trap localized in the n-channel     

2700V4H-SiC结势垒肖特基二极管

在76.2 mm 4H-SiC晶圆上采用厚外延技术和器件制作工艺研制的结势垒肖特基二极管(JBS).在室温下,器件反向耐压达到2700 V.正向开启电压为0.8V,在VF=2V时正向电流密度122 A/cm2,比导通电阻Ron=8.8 mΩ·cm2.得到肖特基接触势垒qφв=1.24 eV,理想因子n=1.     

2.6 kV 4H-SiC lateral DMOSFETs

A 4H-SiC lateral double-implanted metal-oxide-semiconductor (LDMOS) field effect transistor is fabricated in a lightly doped n-epilayer on an insulating 4H-SiC substrate. After depleting through the epilayer, the depletion region continues to move laterally toward the drain. The result is an increase in blocking voltage compared to a vertical DMOSFET fabricated in the same epilayer on a conducting substrate. A blocking voltage of 2.6 kV is obtained, nearly double the highest previously demonstrated blocking voltage for a SiC MOSFET     

1200 V常开型4H-SiC VJFET

用沟槽和离子注入方法在自主外延的4H导通型碳化硅晶圆上研制了垂直沟道结型场效应晶体管(VJFET).在栅电压V<,G>=-10 V时阻断电压达到1 200 V;在V<,G>=2.5 V,V<,D>=2V时的电流密度为395 A/cm<'2>,相应的比导通电阻为5.06 mΩ·cm<'2>.分析发现欧姆接触电阻是导通电阻...     

High-voltage lateral RESURF MOSFETs on 4H-SiC

High-voltage lateral RESURF MOSFETs have been fabricated on 4H-SiC with both nitrogen and phosphorus as source/drain and RESURF region implants. Blocking voltages as high as 1200 V and specific on-resistances of 4 Ω cm² have been obtained, with the high on-resistance attributed to poor inversion layer mobility. Phosphorus is most appropriate for the source/drain implants due to low sheet resistance and contact resistance with low temperature anneals. However, poor activation of low dose phosphorus implants at 1200°C makes nitrogen the preferred choice for the RESURF region     

High current density 800-V 4H-SiC gate turn-off thyristors

4H-SiC gate turn-off thyristors (GTOs) were fabricated using the recently developed inductively-coupled plasma (ICP) dry etching technique. DC and ac characterisation have been done to evaluate forward blocking voltage, leakage current, on-state voltage drop and switching performance. GTOs over 800 V dc blocking capability has been demonstrated with a blocking layer thickness of 7 μm. The dc on-state voltage drops of a typical device at 25 and 300°C were 4.5 and 3.6 V, respectively, for a current density of 1000 A/cm². The devices can be reliably turned on and turned off under an anode current density of 5000 A/cm² without observable degradation     

Improved high-voltage lateral RESURF MOSFETs in 4H-SiC

High-voltage lateral RESURF metal oxide semiconductor field effect transistors (MOSFETs) in 4H-SiC have been experimentally demonstrated, that block 900 V with a specific on-resistance of 0.5 Ω-cm² . The RESURF dose in 4H-SiC to maximize the avalanche breakdown voltage is almost an order of magnitude higher than that of silicon; however this high RESURF dose leads to oxide breakdown and reliability concerns in thin (100-200 nm) gate oxide devices due to high electric field (>3-4 MV/cm) in the oxide. Lighter RESURF doses and/or thicker gate oxides are required in SiC lateral MOSFETs to achieve highest breakdown voltage capability     

1800 V NPN bipolar junction transistors in 4H-SiC

The first high voltage npn bipolar junction transistors (BJTs) in 4H-SiC have been demonstrated. The BJTs were able to block 1800 V in common emitter mode and showed a peak current gain of 20 and an on-resistance of 10.8 mΩ·cm² at room temperature (I_C=2.7 A @ V_CE=2 V for a 1 mm×1.4 mm active area), which outperforms all SiC power switching devices reported to date. Temperature-stable current gain was observed for these devices. This is due to the higher percent ionization of the deep level acceptor atoms in the base region at elevated temperatures, which offsets the effects of increased minority carrier lifetime at high temperatures. These transistors show a positive temperature coefficient in the on-resistance characteristics, which will enable easy paralleling of the devices     

Measured propagation characteristics of coplanar waveguide on semi-insulating 4H-SiC through 800 K

Wireless sensors for high temperature industrial applications and jet engines require RF transmission lines and RF integrated circuits (RFICs) on wide bandgap semiconductors such as SiC. In this paper, the complex propagation constant of coplanar waveguide fabricated on semi-insulating 4H-SiC has been measured through 813 K. It is shown that the attenuation increases 3.4 dB/cm at 50 GHz as the SiC temperature is increased from 300 K to 813 K. Above 500 K, the major contribution to loss is the decrease in SiC resistivity. The effective permittivity of the same line increases by approximately 5% at microwave frequencies and 20% at 1 GHz.     

1000V 4H-SiC VDMOS结构设计与特性研究

设计并优化了一种基于4H-SiC的1000V垂直双扩散金属氧化物半导体场效应晶体管(VDMOS),在留有50%的裕度后,通过Silvaco仿真软件详细研究了器件各项参数与耐压特性之间的关系。经优化,器件的阈值电压为2.3V,击穿电压达1525V,相较于相同耐压条件下的Si基VDMOS,4H-SiC VDMOS的击穿电压提升了12%。此外,击穿时4H-SiC VDMOS表面电场分布相对均匀,最大值为3.4×10⁶V/cm。终端有效长度为15μm,约为Si基VDMOS的6%,总体面积减小了近1/10。并且4H-SiC VDMOS结构简单,与相同耐压条件下的Si基VDMOS相比,未增加额外的工艺步骤,易于实现。     

3000V 10A 4H-SiC结型场效应晶体管的设计与制造

介绍了一种常开型高压4H-SiC JFET的仿真与制造工艺。通过仿真对器件结构和加工工艺进行优化,指导下一步的工艺改进。在N+型4H-SiC衬底上生长掺杂浓度(ND)为1.0×1015 cm-3,厚度为50μm的N-外延层,并采用本实验室开发的SiC JFET工艺进行了器件工艺加工。通过测试,当栅极偏压VG=-6V时,研制的SiC JFET可以阻断3 000V电压;当栅极偏压VG=7V、漏极电压VD=3V时,正向漏极电流大于10A,对应的电流密度为100A/cm2。     

Investigation of lateral spreading current in the 4H-SiC Schottky barrier diode chip

Lateral current spreading in the 4H-SiC Schottky barrier diode(SBD)chip is investigated.The 4H-SiC SBD chips with the same vertical parameters are simulated and fabricated.The results indicate that there is a fixed spreading resistance at on-state in current spreading region for a specific chip.The linear specific spreading resistance at the on-state is calculated to be 8.6 Ω/cm in the fabricated chips.The proportion of the lateral spreading current in total forward current(Psp)is related to an-ode voltage and the chip area.Psp is increased with the increase in the anode voltage during initial on-state and then tends to a stable value.The stable values of Psp of the two fabricated chips are 32％and 54％.Combined with theoretical analysis,the pro-portion of the terminal region and scribing trench in a whole chip(Ksp)is also calculated and compared with Psp.The Ksp val-ues of the two fabricated chips are calculated to be 31.94％and 57.75％.The values of Ksp and Psp are close with each other in a specific chip.The calculated Ksp can be used to predict that when the chip area of SiC SBD becomes larger than 0.5 cm2,the value of Psp would be lower than 10％.     

High temperature physical modeling and verification of a novel 4H-SiC lateral JFET structure

This paper studies the unique behavior of a novel 4H-SiC LJFET structure, featuring the series-connection of a normally-on lateral channel with normally-off vertical channels. A comprehensive physical model is established for the novel structure to explain its different static and dynamic characteristics than the conventional LJFET structure, both at room temperature and high temperature (300 °C). Finite element numerical simulation and experimental measurement are carried out to verify the validity of the established physical model. Good agreements have been achieved among these three sets of results. For the first time, the modeling work studied the detailed operating mechanism and provided valuable design guidelines for SiC LJFET device at temperature as high as 300 °C.     

平面结构4H-SiC BJT击穿特性及终端技术研究

4H-SiC双极晶体管（BJT）主要应用于大功率器件,器件的阻断特性是最重要的性质之一,因此提高器件的耐高压能力非常重要。国内外的高校和研究机构在SiC器件击穿特性的研究方面进行了大量研究。但是目前绝大多数研究都是基于垂直型4H-SiC BJT,而对于平面型4H-SiC BJT击穿特性的研究相对较少。本论文对采取结终端扩展(JTE)和浮空场限环(FFLRs)两种基本结终端结构的平面型器件的击穿特性和击穿机理进行了比较和分析,并在此基础上进行了器件结构优化设计。     

A 475-V high-voltage 6H-SiC lateral MOSFET

High-voltage lateral MOSFET's on 6H- and 4H-SiC have been fabricated with 400-475 V breakdown voltage using the RESURF principle. An MOS electron inversion layer mobility of about 50 cm²/V-s is obtained on 6H-SiC wafers. This mobility is high enough such that the specific on-resistance of the 6H-SiC MOSFET's (~0.29-0.77 Ω-cm²) is limited by the resistance of the drift layer, as desired. However, the implanted drift layer resistance is about ten times higher than expected for the implant dose used. Design and process changes are described to decrease the on-resistance and increase the breakdown voltage. For 4H-SiC, extremely low mobility was obtained, which prevents satisfactory device operation     

3100 V, asymmetrical, gate turn-off (GTO) thyristors in 4H-SiC

A 2-mm×2-mm, 4H-SiC, asymmetrical npnp gate turn-off (GTO) thyristor with a blocking voltage of 3100 V and a forward current of 12 A is reported. This is the highest reported power handling capability of 37 kW for a single device in SiC. The 5-epilayer structure utilized a blocking layer that was 50 μm thick, p-type, doped at about 7-9×10¹⁴ cm^-3. The devices were terminated with a single zone junction termination extension (JTE) region formed by ion-implantation of nitrogen at 650°C. The device was able to reliably turn-on and turn-off 20 A (500 A/cm²) of anode current with a turn-on gain (I_K/I_{G, on}) of 20 and a turn-off gain (I_K/I_{G, off}) of 3.3     

Characteristics of separated-gate JFETs

In the subthreshold region of JFETs a reach-through diode is formed between the top and bottom gates. This has consequences for the application of separated-gate JFETs.     

1200V/100A高温大电流4H-SiC JBS器件的研制

基于SiC结势垒肖特基(JBS)二极管工作原理及其电流/电场均衡分布理论,采用高温大电流单芯片设计技术及大尺寸芯片加工技术,研制了1 200 V/100 A高温大电流4H-SiCJBS二极管.该器件采用优化的材料结构、有源区结构和终端结构,有效提高了器件的载流子输运能力.测试结果表明,当正向导通压降为1.60 V时,其正向电流密度达247 A/cm2(以芯片面积计算).在测试温度25和200℃时,当正向电流为100 A时,正向导通压降分别为1.64和2.50 V;当反向电压为1 200 V时,反向漏电流分别小于50和200μA.动态特性测试结果表明,器件的反向恢复特性良好.器件均通过100次温度循环、168 h的高温高湿高反偏(H3TRB)和高温反偏可靠性试验,显示出优良的鲁棒性.器件的成品率达70％以上.