SiC MOSFETs with thermally oxidized Ta2Si stacked on SiO2 as high-k gate insulator

In this paper, we compare the electrical characteristics of MOS capacitors and lateral MOSFETs with oxidized Ta₂Si (O-Ta₂Si) as a high-k dielectric on silicon carbide or stacked on thermally grown SiO₂ on SiC. MOS capacitors are used to determine the dielectric and interfacial properties of these insulators. We demonstrate that stacked SiO₂/O-Ta₂Si is an attractive solution for passivation of innovative SiC devices. Ta₂Si deposition and oxidation is totally compatible with standard SiC MOSFET fabrication materials and processing. We demonstrate correct transistor operation for stacked O-Ta₂Si on thin thermally grown SiO₂ oxides. However the channel mobility of such high-k MOSFETs must be improved investigating the interface properties further.     

Deposition of uniform Zr-Sn-Ti-O films by on-axis reactivesputtering

We describe the deposition of amorphous Zr-Sn-Ti-O (aZTT) dielectric thin films using conventional on-axis reactive sputtering. Thin films of composition Zr_0.2Sn_0.2Ti_0.6 O₂ have excellent dielectric properties: 40-50-nm thick films with a dielectric constant of 50-70 were obtained, depending on the processing conditions, yielding a specific capacitance of 9-17 fF/μm². Breakdown fields were measured to be 3-5 MV/cm, yielding a figure of merit εε₀E_br=15-30 μC/cm², up to eightfold higher than conventional deposited SiO₂. Leakage currents, measured at 1.0 MV/cm, were in the range 10^-9-10^-7 A/cm². This material appears well-suited for use in Si-IC device technology, for example as storage capacitors in DRAM     

High-Q LaAlO3 dielectric resonator shielded byYBCO-films

We have investigated a dielectric resonator consisting of a single crystalline LaAlO₃-cylinder shielded by a cylindrically shaped copper cavity with endplates made from epitaxial films of YBa₂Cu₃O₇ or niobium. For YBa₂ Cu₃O₇ films unloaded quality factors Q₀ of 4.5·10⁵ at 10 K and 1.3·10⁵ at 77 K were achieved at 11.6 GHz using a compact shielding cavity with a diameter of 15 mm and a height of 3.8 mm. The loss contributions of the dielectric resonator, the normal conducting cylinder wall, and the superconducting endplates, with one of them being separated by a small distance h from the dielectric cylinder, were calculated by modeling the electromagnetic fields of the TE_0νμ-modes. The dielectric loss tangent of the LaAlO ₃-cylinders was found to be 10^-6 at 4.3 K and f=11.6 GHz and to increase slightly with temperature. Moreover, the calculations indicate the tunability of the resonance frequency by changing h over a range of 1 GHz without significant degradation of Q ₀. These resonators are considered to be useful devices for stable oscillators and narrowband filters     

Stack gate PZT/Al2O3 one transistorferroelectric memory

We have developed a single transistor ferroelectric memory using stack gate PZT/Al₂O₃ structure. For the same ~40 Å dielectric thickness, the PZT/Al₂O₃/Si gate dielectric has much better C-V characteristics and larger threshold voltage shift than those of PZT/SiO₂/Si. Besides, the ferroelectric MOSFET also shows a large output current difference between programmed on state and erased off state. The <100 us erase time is much faster than that of flash memory where the switching time is limited by erase time     

Dielectric breakdown mechanism of thin-SiO2 studied bythe post-breakdown resistance statistics

The dielectric breakdown mechanism of SiO₂ has been discussed on the basis of the experimental results of the post-breakdown resistance (R_bd) distribution. We have noticed for the first time that R_bd of SiO₂ in MOS devices is strongly related to the SiO₂ breakdown characteristics such as the polarity dependence or the oxide field dependence of Q_bd. In this paper, we discuss the dielectric breakdown mechanism of SiO₂ from the viewpoint of the statistical correlation between the R _bd distribution, the Q_bd. distribution, and the emission energy just at the SiO₂ breakdown, by changing the stress polarity, stress field, and the oxide thickness. For complete dielectric breakdown, it has been clarified that the R_bd distribution under the substrate electron injection is clearly different from that under the gate electron injection. We have also found that, irrespective of the stress current density, the gate oxide thickness and the stressing polarity, R_bd can be uniquely expressed by the energy dissipation at the occurrence of dielectric breakdown of SiO₂ for the complete breakdown. Furthermore, it has been clarified that R_bd does not depend on the energy dissipation at the occurrence of quasidielectric breakdown     

Effects of high-κ gate dielectric materials on metal andsilicon gate workfunctions

The dependence of metal and polysilicon gate work-functions on the underlying gate dielectric in advanced MOS gate stacks is explored. We observe that the metal workfunctions on high-κ dielectrics differ appreciably from their values on SiO₂ or in a vacuum. We also show the first application of the interface dipole theory on the metal-dielectric interface and obtained excellent agreement with experimental data. Important parameters such as the slope parameters for SiO₂, Si₃N₄, ZrO₂, and HfO ₂ are extracted. In addition, we also explain the weaker dependence of n+ and p+ polysilicon gate workfunctions on the gate dielectric. Challenges for gate workfunction engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future CMOS technology incorporating high-κ gate dielectrics     

Low Subthreshold Swing HfLaO/Pentacene Organic Thin-Film Transistors

We have integrated a high-kappa HfLaO dielectric into pentacene-based organic thin-film transistors. We measured good device performance, such as a low subthreshold swing of 0.078 V/dec, a threshold voltage of -1.3 V, and a field-effect mobility of 0.71cm²/ Vldrs . This occurred along with an ON-OFF state drive current ratio of 1.0 times 10⁵, when the devices were operated at only 2 V. The performance is due to the high gate-capacitance density of 950 nF/cm² that is given by the HfLaO dielectric, which is achieved at an equivalent oxide thickness of only 3.6 nm with a low leakage current of 5.1 times 10^-7 at 2 V.     

Dielectric deposition process for Cu/SiO2 integration in a dual damascene interconnection architecture

A challenge to integrate Cu in device interconnections is to avoid Cu diffusion into silicon active zone that could seriously damage device performance, and into interlevel dielectric that could induce shorts or degrade dielectric performance. This paper relates the integration of Cu-CVD with SiO₂. Structures studied are SiO₂ deposited on Cu-CVD, and SiO₂/SiN/Cu structure: a thin SiN layer is deposited on Cu before SiO₂ to act as diffusion barrier and as an etch stop during the interconnect structure patterning. Both SiO₂ and SiN dielectric processes are made in plasma-enhanced chemical vapor deposition processes, from SiH₄ precursor with addition of, respectively, N₂O or NH₃. Cu contamination is shown to occur during the dielectric deposition onto Cu, and is enhanced by the fluorine presence in the deposition chamber. Deposition processes were evaluated in order to lower Cu contamination in the dielectric bulk. On an other hand, a noticeable degradation in Cu layer resistance was evidenced after dielectric deposition due to copper contamination during the dielectric deposition process. This issue can be addressed by the optimization of the dielectric deposition process.     

Ferroelectric materials for 64 Mb and 256 Mb DRAMs

The authors have studied the feasibility of using ferroelectric materials as the capacitor dielectric in the one-transistor memory cells for 64-Mb and 256-Mb DRAMs. They have performed an intensive literature search and analysis. They discuss the crystal structure of the materials reviewed, their hysteresis curve, temperature dependence of the spontaneous polarization, leakage current, dielectric breakdown, reliability, ageing, and fatigue. The authors examine the charge storage capacity in a 1-T DRAM cell and analyze a number of ferroelectric materials for their potential use as the dielectric in 64-Mb and 256-Mb DRAM capacitors, focusing on projected requirements for the electrical parameters and preferred material characteristics. Of the materials examined, those that appear to hold the greatest promise for 64-Mb and 256-Mb DRAMs are the paraelectric phase compositions of (Pb,La)TiO₃ (PLT) and (Pb,La)(Zr,Ti)O₃ (PLZT). Pb(Mg,Nb)O₃ (PMN) is also attractive because it is paraelectric, but it may not be able to achieve the required charge densities when deposited as a thin film     

Electrical characteristics of high quality La2O3 gate dielectric with equivalent oxide thickness of 5 Å

Electrical and reliability properties of ultrathin La₂O ₃ gate dielectric have been investigated. The measured capacitance of 33 Å La₂O₃ gate dielectric is 7.2 μF/cm² that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 Å. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm² at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3×10¹⁰ eV^-1/cm², and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO₂      

Effect of the nitrous oxide plasma treatment on the MIM capacitor

We report the demonstration of near zero voltage coefficient of capacitance (VCC) by exposing the silicon nitride dielectric of the metal-insulator-metal capacitor (MIM) to nitrous oxide (N₂O) plasma. Oxidization in the N₂O plasma enhanced the hard breakdown field, whereby an excess of 9 MV/cm was achieved. In addition, low-temperature coefficient of capacitance (TCC) of < 20 ppm/K and high dielectric constant ⩾ 6.5 were preserved     

High quantum efficiency and narrow absorption bandwidth of thewafer-fused resonant In0.53Ga0.47As photodetectors

We demonstrate greater than 90% quantum efficiency in an In_0.53Ga_0.47As photodetector with a thin (900 Å) absorbing layer. This was achieved by inserting the In_0.53 Ga_0.47As/InP epitaxial layer into a microcavity composed of a GaAs/AlAs quarter-wavelength stack (QWS) and a Si/SiO₂ dielectric mirror. The 900-Å-thick In_0.53 Ga_0.47As layer was wafer fused to a GaAs/AlAs mirror, having nearly 100% power reflectivity. A Si/SiO₂ dielectric mirror was subsequently deposited onto the wafer-fused photodiode to form an asymmetric Fabry-Perot cavity. The external quantum efficiency and absorption bandwidth for the wafer-fused RCE photodiodes were measured to be 94±3% and 14 nm, respectively. To our knowledge, these wafer-fused RCE photodetectors have the highest external quantum efficiency and narrowest absorption bandwidth ever reported on the long-wavelength resonant-cavity-enhanced photodetectors     

Performance Improvement of $hbox{Sm}_{2}hbox{O}_{3}$ MIM Capacitors by Using Plasma Treatment After Dielectric Formation

In this letter, we investigate the dependence of the performance of metal-insulator-metal (MIM) capacitors with Sm₂O₃ dielectric on plasma treatment (PT) performed before Sm₂O₃ deposition, after Sm₂O₃ deposition, or both before and after Sm₂O₃ deposition. By performing PT in N₂ ambient (PTN) after Sm₂O₃ dielectric formation, the effective quadratic voltage coefficient of capacitance (VCC) can be reduced from 498 to 234 ppm/V² and the effective linear VCC can be reduced from 742.3 to 172 ppm/V for MIM capacitor with Sm₂O₃ dielectric having a capacitance density of ~ 7.5 fF/mum². The leakage current density at +3.3 V can be reduced from 3.44 10^-7 to 1.60 times 10^-8 A/cm² by performing PTN in both before and after Sm₂O₃ deposition. PTN after dielectric formation is an effective way to improve the performance of high-kappa dielectric MIM capacitors for RF and analog/mixed signal IC applications.     

Fabrication of low dielectric constant materials for ULSImultilevel interconnection by plasma ion implantation

High dose-rate plasma ion implantation (PII) has been utilized to produce low dielectric constant (k) SiO₂ films for high quality interlayer dielectrics. The SiO₂ films are fluorine-doped/carbon-doped by PII with CF₄ plasma in an inductively-coupled plasma (ICP) reactor. It is found that the use of CF ₄ doping results in exceptional dielectric properties which differ significantly from fluorinated SiO₂. The dielectric constant of the SiO₂ film is reduced from 4.1 to 3.5 after 5 minute PII, other electrical parameters such as bulk resistivity and dielectric breakdown strength are also improved     

Direct tunneling gate leakage current in transistors with ultrathinsilicon nitride gate dielectric

We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si₃N₄) gate dielectric formed by the jet-vapor deposition (JVD) technique. The tunneling mechanisms in the N- and PMOSFETs were clarified. The electron and hole tunneling masses and barrier potentials for the different tunneling mechanisms mere extracted from measured data using a new semi-empirical model. This model was used to project the scaling limits of the JVD Si ₃N₄ gate dielectric based on the supply voltages for the various technology nodes and the maximum tolerable direct tunneling gate current for high-performance and low-power applications     

Dual-metal gate CMOS technology with ultrathin silicon nitride gatedielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si₃N₄) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO₂) are observed     

Furnace nitridation of thermal SiO2 in pureN2O ambient for ULSI MOS applications

Furnace nitridation of thermal SiO₂ in pure N₂ O ambient for MOS gate dielectric application is presented. N₂O-nitrided thermal SiO₂ shows much tighter distribution in time-dependent dielectric breakdown (TDDB) characteristics than thermal oxide. MOSFETs with gate dielectric prepared by this method show improved initial performance and enhanced device reliability compared to those with thermal gate oxide. These improvements are attributed to the incorporation of a small amount of nitrogen (~1.5 at.%) at the Si-SiO₂ interface without introducing H-related species during N₂O nitridation     

Highly reliable SiO2/Si3N4 stackeddielectric on rapid-thermal-nitrided rugged polysilicon for high-densityDRAM's

Experimental results are presented demonstrating that by using rapid thermal nitridation (RTN) of rugged poly-Si surface prior to Si ₃N₄ deposition, the quality and reliability of reoxidized Si₃N₄ dielectric (ON dielectric with an effective oxide thickness of about 35 Å) can be significantly improved over ON films on rugged poly-Si without RTN treatment. These improvements include significantly reduced defect-related dielectric breakdown, 10³ × increase in TDDB lifetime, lower leakage current, and suppressed electron-hole trapping and capacitance loss during stress     

Field singularities at metal-dielectric wedges

The wedges discussed are the dielectric wedge, the metallic90degcorner on a dielectric plane, and the adjacent90degmetallic and dielectric corners. The field components perpendicular to the edge may become infinite according to a law (1/r^{n}). Numerical data are given forn, and plots of lines of force ofbar{e}(orbar{h}) are shown.     

Organic thin-film field-effect transistors with MoO3/Al electrode and OTS/SiO2 bilayer gate insulator

An organic thin-film transistor (OTFTs) having OTS/SiO₂ bilayer gate insulator and MoO₃/Al electrode configuration between gate insulator and source–drain (S–D) electrodes has been investigated. Thermally grown SiO₂ layer is used as the OTFT gate dielectric and copper phthalocyanine (CuPc) for an active layer. We have found that using silane coupling agents, octadecyltrichlorosilane (OTS) on SiO₂, surface energy of SiO₂ gate dielectric is reduced; consequently, the device performance has been improved significantly. This OTS/SiO₂ bilayer gate insulator configuration increases the field-effect mobility, reduces the threshold voltage and improves the on/off ratios simultaneously. The device with MoO₃/Al electrode has similar source–drain current (I_DS) compared to the device with Au electrode at same gate voltage. Our results indicate that using double-layer of insulator and modified electrode is an effective way to improve OTFT performance.