全耗尽CMOS/SOI工艺

对全耗尽CMOS/SOI工艺进行了研究,成功地开发出成套全耗尽 CMOS/SOI抗辐照工艺.其关键工艺技术包括:氮化H2-O2合成薄栅氧、双栅和注Ge硅化物等技术.经过工艺投片,获得性能良好的抗辐照CMOS/SOI器件和电路(包括101级环振、2000门门海阵列等),其中,nMOS:Vt=0.7V,Vds=4.5～5.2V,μeff=465cm2/(V*s),pMOS:Vt=-0.8V,Vds=-5～-6.3V,μeff=264cm2/(V*s).当工作电压为5V时,0.8μm环振单级延迟为45ps.     

45ps的超高速全耗尽CMOS/SOI环振

亚微米全耗尽SOI(FDSOI)CMOS器件和电路经过工艺投片,取得良好的结果,其中工作电压为5V时,0.8μm全耗尽CMOS/S0I101级环振的单级延迟仅为45ps;随着硅层厚度的减薄和沟道长度的缩小,电路速度得以提高,0.8μm全耗尽CMOS/SOI环振比0.8μm部分耗尽CMOS/SOI环振快30%,比1μm全耗尽CMOS/SOI环振速度提高15%.     

全耗尽CMOS/SOI工艺

对全耗尽 CMOS/ SOI工艺进行了研究 ,成功地开发出成套全耗尽 CMOS/ SOI抗辐照工艺 .其关键工艺技术包括 :氮化 H2 - O2 合成薄栅氧、双栅和注 Ge硅化物等技术 .经过工艺投片 ,获得性能良好的抗辐照 CMOS/ SOI器件和电路 (包括 10 1级环振、2 0 0 0门门海阵列等 ) ,其中 ,n MOS:Vt=0 .7V,Vds=4 .5～ 5 .2 V,μeff=4 6 5 cm2 / (V· s) ,p MOS:Vt=- 0 .8V ,Vds=- 5～ - 6 .3V,μeff=2 6 4 cm2 / (V· s) .当工作电压为 5 V时 ,0 .8μm环振单级延迟为 4 5 ps     

45ps的超高速全耗尽CMOS/SOI环振

亚微米全耗尽 SOI( FDSOI) CMOS器件和电路经过工艺投片 ,取得良好的结果 ,其中工作电压为 5V时 ,0 .8μm全耗尽 CMOS/ SOI1 0 1级环振的单级延迟仅为 45ps;随着硅层厚度的减薄和沟道长度的缩小 ,电路速度得以提高 ,0 .8μm全耗尽 CMOS/ SOI环振比 0 .8μm部分耗尽 CMOS/ SOI环振快 30 % ,比 1 μm全耗尽 CMOS/ SOI环振速度提高 1 5% .     

部分耗尽CMOS/SOI工艺

对部分耗尽 CMOS/ SOI工艺进行了研究 ,成功地开发出成套部分耗尽 CMOS/ SOI抗辐照工艺 .其关键工艺技术包括 :PBL (Poly- Buffered L OCOS)隔离、沟道工程和双层布线等技术 .经过工艺投片 ,获得性能良好的抗辐照 CMOS/ SOI器件和电路 (包括 10 1级环振、 5 0 0 0门门海阵列和 6 4K CMOS/ SOI静态存储器 ) .其中 ,NMOS:Vt=1.2 V ,BVds=7.5— 9V ,μeff=42 5 cm2 / (V· s) ,PMOS:Vt=- 0 . 9V,BVds=14— 16 V,μeff=2 40 cm2 /(V· s) ,当工作电压为 5 V时 ,0 .8μm环振单级延迟为 10 6 ps,SOI 6 4K CMOS静态存储器数据读取时间为 40 ns     

0.8 μm PDSOI CMOS器件和环振电路研究

研究了0.8μm部分耗尽绝缘体上硅(PDSOI)CMOS器件和电路,开发出成套的0.8μmPDSOI CMOS工艺.经过工艺投片,获得了性能良好的器件和电路.其中,当工作电压为5 V时,基于浮体SOI CMOS技术的0.8μm 101级环振单级延时为49.5 ps;基于H型栅体引出SOI CMOS技术的0.8μm 101级环振单级延时为158 ps.同时,对PDSOI CMOS器件的特性,如浮体效应、背栅特性、反常亚阈值斜率、击穿特性和输出电导变化等进行了讨论.     

采用新的抬高源漏工艺技术制作的全耗尽SOI CMOS器件和电路

采用新的工艺技术,成功研制了具有抬高源漏结构的薄膜全耗尽SOI CMOS器件.详细阐述了其中的关键工艺技术.器件具有接近理想的亚阈值特性,nMOSFETs和pMOSFETs的亚阈值斜率分别为65和69mV/dec.采用抬高源漏结构的1.2μm nMOSFETs的饱和电流提高了32%,pMOSFETs的饱和电流提高了24%.在3V工作电压下101级环形振荡器电路的单级门延迟为75ps.     

0.5μm SOI CMOS器件和电路

研究了0.5μm SOI CMOS器件和电路,开发出成套的0.5μm SOI CMOS工艺.经过工艺投片,获得了性能良好的器件和电路,其中当工作电压为3V时,0.5μm 101级环振单级延迟为42ps.同时,对部分耗尽SOI器件特性,如“浮体”效应、“kink”效应和反常亚阈值特性进行了讨论.     

N+多晶硅栅薄膜全耗尽SOI CMOS器件与电路的研究

选用SIMOX(Separation by Implantation of Oxygen)衬底材料,对全耗尽SOI CMOS工艺进行了研究,开发出了N 多晶硅栅全耗尽SOI CMOS器件及电路工艺,获得了性能良好的器件和电路。nMOS和pMOS的驱动电流都比较大,且泄漏电流很小,在工作电压为3V时,1．2μm101级环振的单级延迟仅为50．5ps。     

薄膜全耗尽SOI CMOS器件和电路

对全耗尽SOI(FD SOI)CMOS器件和电路进行了研究,硅膜厚度为70nm.器件采用双多晶硅栅结构,即NMOS器件采用P+多晶硅栅,PMOS器件采用N+多晶硅栅,在轻沟道掺杂条件下,得到器件的阈值电压接近0.7V.为了减小源漏电阻以及防止在沟道边缘出现空洞(Voids),采用了注Ge硅化物工艺,源漏方块电阻约为5.2Ω/□.经过工艺流片,获得了性能良好的器件和电路.其中当工作电压为5V时,0.8μm 101级环振单级延迟为45ps.     

超高速CMOS/SOI51级环振电路的研制

利用CMOS/SOI工艺在4英寸SIMOX材料上成功制备出沟道长度为1μm、器件性能良好的CMOS/SOI部分耗尽器件和电路,从单管的开关电流比看,电路可以实现较高速度性能的同时又可以有效抑制泄漏电流.所研制的51级CMOS/SOI环振电路表现出优越的高速度性能,5V电源电压下单门延迟时间达到92ps,同时可工作的电源电压范围较宽,说明CMOS/SOI技术在器件尺寸降低后将表现出比体硅更具吸引力的应用前景.     

Submicrometer CMOS devices in zone-melting-recrystallized SOI films

CMOS devices with effective channel lengths ranging from 0.7 to 4.0 µm have been fabricated in zone-melting-recrystallized (ZMR) silicon-on-insulator (SOI) films prepared by the graphite-strip-heater technique. Low-temperature processing was utilized to minimize dopant diffusion along subboundaries in the films. Both n- and p-channel devices have low leakage current (<0.1-pA/µm channel width) and good subthreshold characteristics. For ring oscillators with a transistor channel length of 0.8 µm, the propagation delay is 95 ps at a supply voltage of 5 V.     

Self-aligned silicide technology for ultra-thin SIMOX MOSFETs

The salicide technology using rapid thermal annealing was applied to MOSFETs on thin-film SOI. Since the SOI film was limited to a thickness of less than 100 nm, the silicidation reaction between Ti and Si atoms on the SOI surface exhibited new features that depended on the initial thickness of the deposited Ti. There was an optimum thickness of as-deposited Ti on silicidation due to the restricted thickness of the Si layer. Beyond the optimum point, the region adjacent to the silicided Si layer works as a Si source to assure stoichiometric TiSi₂. The subthreshold slopes and carrier mobilities were not changed by the salicide process. Junction leakage characteristics were slightly degraded; however, the change was small enough for device application. The influence on AC characteristics was well demonstrated for a high-speed CMOS ring oscillator with a gate length of 0.7 μm. The minimum delay time/stage was 46 ps/stage at 5 V. This gives 1.8 times higher speed operation than the controlled bulk CMOS ring oscillators with the same design rule     

多晶硅双栅全耗尽SOI CMOS器件与电路

对多晶硅双栅全耗尽SO I CM O S工艺进行了研究,开发出了1.2μm多晶硅双栅全耗尽SO I CM O S器件及电路工艺,获得了性能良好的器件和电路。NM O S和PM O S的阈值电压绝对值比较接近,且关态漏电流很小,NM O S和PM O S的驱动电流分别为275μA/μm和135μA/μm,NM O S和PM O S的峰值跨导分别为136.85 m S/mm和81.7 m S/mm。在工作电压为3 V时,1.2μm栅长的101级环振的单级延迟仅为66 ps。     

Impact of self-heating and thermal coupling on analog circuits inSOI CMOS

This paper examines the influence of the static and dynamic electrothermal behavior of silicon-on-insulator (SOI) CMOS transistors on a range of primitive analog circuit cells. In addition to the more well-known self-heating close-range thermal coupling effects are also examined. Particular emphasis is given to the impact of these effects on drain current mismatch due to localized temperature differences. Dynamic electrothermal behavior in the time and frequency domains is also considered, measurements and analyses are presented for a simple amplifier stage, current mirrors, a current output D/A converter, and ring oscillators fabricated in a 0.7-μm SOI CMOS process. It is shown that circuits which rely strongly on matching, such as the current mirrors or D/A converter, are significantly affected by self-heating and thermal coupling. Anomalies due to self-heating are also clearly visible in the small-signal characteristics of the amplifier stage. Self-heating effects are less significant for fast switching circuits. The paper demonstrates how circuit-level simulations can be used to predict undesirable nonisothermal operating conditions during the design stage     

0．8μm SOI CMOS技术及电路研制

SOI CMOS技术在一些特殊应用领域中有着体硅无法比拟的优势文中叙述采用SIMOX材料和0.8μm SOI CMOS工艺加固技术成功研制出抗辐射性能较好的器件和电路,并且给出了SOI CMOS器件的特性随辐照总剂量的变化关系,试验电路通过了总剂量500 Krad(Si)钴60γ射线辐照实验。     

SOI/CMOS circuits fabricated in zone-melting-recrystallized Si films on SiO2-coated Si substrates

A CMOS test circuit chip containing six arrays of 360 to 533 parallel transistors, two 31-stage ring oscillators, and two inverter chains has been designed for evaluating SOI wafers prepared by using the graphite strip-heater technique for zone-melting recrystallization of poly-Si films on SiO2-coated Si substrates. One 2-in-diameter wafer has been evaluated in detail by testing all the circuits on each of 98 chips fabricated in the recrystallized film. These measurements reveal a good yield of functional circuits, and most of the failures can be explained by obvious metallization defects. The operating characteristics of each type of circuit are quite uniform from chip to chip. For the ring oscillators, which have a 5 µm gate length and fan in and out of one, at a supply voltage of 5 V the switching delay time is about 2 n s per stage and the power-delay product is 0.2-0.3 pJ per stage.