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1.
A 10 Gb/s BiCMOS adaptive cable equalizer   总被引:3,自引:0,他引:3  
A 10 Gb/s adaptive equalizer IC using SiGe BiCMOS technology is described. The circuit consists of the combination of an analog equalizer and an adaptive feedback loop for minimizing the inter-symbol interference (ISI) for a variety of cable characteristics. The adaptive loop functions using a novel slope-detection circuit which has a characteristic that correlates closely with the amount of ISI. The chip occupies an area of 0.87 mm/spl times/0.81 mm and consumes a power of 350 mW with 3.3 V power supply. This adaptive equalizer is able to compensate for a cable loss up to 22dB at 5 GHz while maintaining a low bit-error rate.  相似文献   

2.
The architectural and circuit design aspects of a mixed analog/digital very large scale integration (VLSI) motion detection chip based on models of the insect visual system are described. The chip comprises two one-dimensional 64-cell arrays as well as front-end analog circuitry for early visual processing and digital control circuits. Each analog processing cell comprises a photodetector, circuits for spatial averaging and multiplicative noise cancellation, differentiation, and thresholding. The operation and configuration of the analog cells is controlled by digital circuits, thus implementing a reconfigurable architecture which facilitates the evaluation of several newly designed analog circuits. The chip has been designed and fabricated in a 1.2-μm CMOS process and occupies an area of 2×2 mm2  相似文献   

3.
A continuous-time forward equalizer with one adaptive zero and a seventh-order linear-phase low-pass filter are described. The forward equalizer cancels precursor intersymbol interference (ISI). A mixed-signal four-tap RAM decision-feedback equalizer (DFE) is also included on the prototype to cancel the postcursor ISI. Both precursor and postcursor ISI are canceled in the analog domain. The adaption is done digitally. The low-pass filter and forward equalizer together occupy 6.7 mm2 in a 1 μm CMOS process. They dissipate 280 mW from a 5 V supply when operating at 80 Mb/s. Including the RAM-DFE, the entire chip occupies 11.2 mm2 and dissipates 630 mW  相似文献   

4.
This paper describes a fully differential 1-tap decision feedback equalizer in 0.18-$muhbox m$SiGe BiCMOS technology. The circuit is capable of equalizing NRZ data up to 40 Gb/s. A look-ahead architecture is employed with modifications to reduce complexity in the high-speed clock distribution. An analog differential voltage controls the tap weights. The design is fabricated in 0.18-$muhbox m$SiGe BiCMOS technology with a 160-GHz$f_T$. It occupies an area of 1.5 mm$,times ,$1 mm and operates from a 3.3-V supply with 230-mA current. It is the first feedback equalizer at 40 Gb/s.  相似文献   

5.
A CMOS analog equalizer is designed to meet the different high speed communication specifications,such as USB 2.0,PCI-E and rapid IO.The proposed circuit architecture could facilitate the wide frequency scale ranging from 1 to 3.125 Gbps by adjusting the locations of pole and zero,so that the circuit can change its response accordingly as the channel characteristic alters.In order to balance the parasitic capacitors in the internal point,symmetric switches are addressed to generate the equal load for dif...  相似文献   

6.
A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. The 20-MHz sixth-order Bessel filter and second-order equalizer operate from 5 V and generate only 0.24% (-52 dB) of total harmonic distortion when processing 2-Vpp differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36 Mb/s and is built in a 1.5-μm, 4-GHz BiCMOS technology  相似文献   

7.
An adaptive analog noise-predictive decision-feedback equalizer   总被引:1,自引:0,他引:1  
In this paper, an adaptive noise-predictive decision-feedback equalizer (NPDFE) is presented. The NPDFE architecture and its implementation are described. The NPDFE consists of an analog finite-impulse-response (FIR) forward equalizer, a recursive analog equalizer for noise prediction, and a decision-feedback equalizer (DFE). The recursive equalizer reduces noise enhancement and improves the signal-to-noise ratio (SNR) at the decision slicer input. The prototype targets a magnetic recording channel modeled by a Lorentzian impulse response. Measured results show that compared to a conventional DFE with FIR forward equalizer, the NPDFE achieves a SNR improvement of about 2 dB with PW50=2.5T. The NPDFE consumes 130 mW at a data rate of 100 Mb/s and occupies 1.3 mm2 of die area in a 0.5-μm CMOS process  相似文献   

8.
A 50-Gb/s low-power analog equalizer has been realized in 65-nm CMOS technology. This equalizer adopts the proposed transformer feedback technique to achieve a peaking gain of 18 dB at 25 GHz and low-power dissipation. The whole equalizer without the output buffer consumes 10 mW from a 1-V supply. The chip occupies 0.35 times 0.27 mm2. For a 50-Gb/s pseudorandom bit sequence of 27 - 1 , the measured bit error rate is less than 10-12, and the measured maximum root-mean-square and peak-to-peak jitters are 2.7 and 12.4 ps, respectively.  相似文献   

9.
A passive CMOS switched-capacitor finite-impulse-response equalizer is described. A sampling rate of 200 MS/s is achieved by six time-interleaved channels. Nonlinear parasitic capacitance scales the equalized output but does not affect the zero locations of the equalizer for a binary or ternary data signal. The 4-tap equalizer prototype is fully differential. At 200 MS/s, the equalizer dissipates 19.5 mW, which is virtually all consumed by clock drivers, and occupies an active area of 1.3 mm2 in a 0.35 mum CMOS process  相似文献   

10.
本文提出了一种支持多标准的具有系数可调的均衡器和宽跟踪能力的时钟数据恢复电路。基于对系统参数和一阶 bang-bang 时钟数据恢复电路的环路特性分析,推导出电路设计参数。考虑到抖动性能,追踪能力以及芯片面积,文中采用了一阶数字滤波器和6-bit DAC以及高线性度的相位插值器实现了高相位调整精度和小面积的时钟恢复电路,同时该结构实现了±2200ppm的频偏跟踪能力,使得该结构适用于不同源的高速串行传输系统,尤其是内嵌时钟结构。该设计已经在55nm CMOS工艺上流片验证,测试结果显示符合误码率的要求以及抖动容忍规范。该测试芯片整体面积是0.19mm2,其中时钟恢复电路只占0.0486mm2 而且该电路工作在5Gbps,供电电压为1.2V时,只消耗30mW。  相似文献   

11.
Crosstalk between neighboring channels can have significant impact on system bit-error rate (BER) as serial I/O data rates scale above 10 Gb/s. This paper presents receive-side circuitry which merges the cancellation of both near-end and far-end crosstalk (NEXT/FEXT) and can automatically adapt to different channel environments and variations in process, voltage, and temperature. NEXT cancellation is realized with a novel 3-tap FIR filter which combines two traditional FIR filter taps and a continuous-time band-pass filter IIR tap for efficient crosstalk cancellation, with all filter tap coefficients automatically determined via an on-die sign–sign least-mean-square (SS-LMS) adaptation engine. FEXT cancellation is realized by coupling the aggressor signal through a differentiator circuit whose gain is automatically adjusted with a power-detection-based adaptation loop. A prototype fabricated in a general purpose 65-nm CMOS process includes the adaptive NEXT and FEXT circuitry, along with a continuous-time linear equalizer (CTLE) to compensate for frequency-dependent channel loss. Enabling the crosstalk cancellation circuitry while operating at 10 Gb/s over coupled 4-in FR4 transmission line channels with NEXT and FEXT aggressors opens a previously closed eye and allows for a 0.2 UI timing margin at a BER = 10?9. Total power including the NEXT/FEXT crosstalk cancellation circuitry, CTLE, and high-speed output buffer is 34.6 mW, and the core circuit area occupies 0.3 mm2.  相似文献   

12.
This paper presents the design of a 1 Gb/s 5-tap T/2 fractionally-spaced equalizer. The T/2 delay lines are based on third-order linear-phase double terminated sections that offer a tunable group delay of 500 ps with less than 10% ripple and a 3 dB bandwidth greater than 600 MHz. Furthermore, the equalizer architecture introduces a broadband summing circuit using a transimpedance $I/V$ converter that increases the bandwidth by a factor of 3.6 over a conventional resistive loaded analog adder. The topology's performance is demonstrated in the equalization of 1 Gb/s binary data through CAT5e twisted-pair cables for up to 23 meters. The vertical eye-opening increases from 0% to 58%. Implemented in CMOS 0.35 $mu{hbox{m}}$, the transversal equalizer occupies an area of 26 ${hbox{mm}}^{2}$ and consumes 32 mA.   相似文献   

13.
In this paper, we present the analog circuit design and implementation of the components of an adaptive neuromorphic olfaction chip. A chemical sensor array employing carbon black composite sensing materials with integrated signal processing circuitry forms the front end of the chip. The sensor signal processing circuitry includes a dc offset cancellation circuit to ameliorate loss of measurement range associated with chemical sensors. Drawing inspiration from biological olfactory systems, the analog circuits used to process signals from the on-chip odor sensors make use of temporal "spiking" signals to act as carriers of odor information. An on-chip spike time dependent learning circuit is integrated to dynamically adapt weights for odor detection and classification. All the component subsystems implemented on chip have been successfully tested in silicon  相似文献   

14.
张明科  胡庆生 《电子学报》2017,45(7):1608-1612
本文介绍了应用于背板通信系统中均衡器的设计与实现.该均衡器采用连续时间线性均衡器(Continuous Time Linear Equalizer,CTLE)和2抽头判决反馈均衡器(Decision Feedback Equalizer,DFE)的组合结构来消除信道码间干扰中的前标分量和后标分量.在设计中,CTLE采用双路均衡器结构补偿信道不同频率的损耗,减小了电路的面积和功耗;DFE采用半速率预处理结构来缓解传统DFE结构中关键反馈路径的时序限制,并采用模拟最小均方(Least Mean Square,LMS)算法电路控制DFE系数的自适应.电路采用IBM 0.13μm BiCMOS工艺设计并实现,测试结果表明对于经过18英寸背板后眼图完全闭合的24Gb/s的信号,均衡后的眼图水平张开度达到了0.81UI.整个均衡器芯片包括焊盘在内的芯片面积为0.78×0.8mm2,在3.3V的电源电压下,功耗为624mW.  相似文献   

15.
A mixed analog/digital chip that forms the core of a medium-speed modem for use on the public switched telephone network is described. It meets CCITT and AT&T requirements for data transmission at 2400 and 1200 b/s, and the AT&T requirement for 300-b/s operation. The chip is implemented in a 1.75-μm analog CMOS process and occupies 32.4 mm 2. The device is powered by a single +5-V supply and consumes less than 115 mW. The architecture and circuit implementation are described, and experimental results are given  相似文献   

16.
Analog circuit techniques can be beneficially applied to reduce the circuit complexity and power consumption of motion estimation processors for digital video encoding. However, analog circuits are sensitive to mismatch which affects motion estimation. This paper presents the design of an analog motion estimation processor which overcomes these limitations. A novel architecture is described featuring pixel reuse and input offset error cancellation. The proof-of-concept realization was fabricated in 0.8-/spl mu/m CMOS, and operates on 4/spl times/4 pixel blocks and a search area of 8/spl times/8 pixels. However, the architecture is scalable to larger block sizes and more advanced technologies. Measured results for various QCIF video sequences at 15-f/s showed excellent PSNR performance. The prototype dissipates 0.9 mW of power from a single 3-V power supply and occupies an area of 0.95 mm/sup 2/. Energy consumption is 1.51 nJ per motion vector.  相似文献   

17.
The authors report a MOSFET-C variable bump equalizer architecture in MOS technology. The architecture is CAD-compatible in that it has a fixed physical layout, yet it achieves independent and continuous programmability of the three equalizer parameters ω0 (center frequency), BW (bandwidth), and G (gain), using DC control voltages. To compensate for process and temperature variations the equalizer is tuned using a novel and simple master-slave automatic tuning scheme based on a switched-capacitor resistor in a gain control loop. The nonideal effects of the equalizer circuit due to finite amplifier gain bandwidth are studied, and a test chip is fabricated using the MOSIS 2-μm p-well double-poly CMOS process to verify the performance. The equalizer with the automatic tuning circuit occupies 1.25 mm2 and operates from ±5-V power supplies. It dissipates 60 mW and provides wide tuning ranges for ω0, BW, and G with less than 2.8% change in ω0 over a 40°C temperature range  相似文献   

18.
A sample-and-hold amplifier designed for the front end of high-speed low-power analog-to-digital converters employs a BiCMOS sampling switch and a low-voltage amplifier to achieve a sampling rate of 200 MHz while allowing input/output voltage swings of 1.5 V with a 3-V supply. The circuit also incorporates a cancellation technique to relax the trade-off between the hold-mode feedthrough and the sampling speed. Fabricated in a 20-GHz 1-μm BiCMOS technology, an experimental prototype exhibits a harmonic distortion of -65 dB with a 10-MHz analog input and occupies an area of 220×150 μm2. The measured feedthrough is -52 dB for a 50-MHz analog input and the droop rate is 40 μV/ns  相似文献   

19.
Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size.  相似文献   

20.
A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13μm CMOS process.The circuit consists of the combination of equalizer amplifier,limiter amplifier and adaptation loop.The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics.In addition,an offset cancellation loop is used to alleviate the offset influence of the signal path.The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply.Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter.  相似文献   

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