基于等离子体氮化工艺的超薄栅氧化膜的电学特性和可靠性

介绍了利用MMT等离子体氮化工艺和炉管NO退火氮化工艺制备的超薄栅介质膜的电学特性和可靠性.结合两种氮化工艺在栅介质膜中形成了双峰和单峰的氮分布.通过漏极电流、沟道载流子和TDDB的测试,发现栅介质膜中双峰的氮分布可以有效提高器件的电学特性,更为重要的是可以极大提高器件的击穿特性.这指明了延长掺氮氧化膜在超大规模集成电路器件栅介质层中应用的寿命,使之有可能进一步跟上技术的发展.     

基于等离子体氮化工艺的超薄栅氧化膜的电学特性和可靠性

介绍了利用MMT等离子体氮化工艺和炉管NO退火氮化工艺制备的超薄栅介质膜的电学特性和可靠性. 结合两种氮化工艺在栅介质膜中形成了双峰和单峰的氮分布. 通过漏极电流、沟道载流子和TDDB的测试,发现栅介质膜中双峰的氮分布可以有效提高器件的电学特性,更为重要的是可以极大提高器件的击穿特性. 这指明了延长掺氮氧化膜在超大规模集成电路器件栅介质层中应用的寿命,使之有可能进一步跟上技术的发展.     

栅介质氧化层缺失缺陷的形成原因及解决方案

氮氧化技术是45 nm及以下技术节点栅介质制备的关键工艺,严格控制由氮氧化工艺所诱发的界面缺陷是提高栅介质质量的重点.研究了形成栅介质氧化层缺失缺陷的原因,并提出了解决方案.结果表明,原位水蒸气生成(ISSG)热氧化形成栅介质氧化层后的实时高温纯惰性氮化热处理工艺是形成栅介质氧化层缺失缺陷的主要原因;在实时高温纯惰性氮化热处理工艺中引入适量的O2,可以消除栅介质氧化层的缺失缺陷.数据表明,引入适量O2后,栅介质氧化层的界面陷阱密度(Dit)和界面总电荷密度(ΔQtot)分别减少了12.5％和26.1％;pMOS器件负偏压不稳定性(NBTI)测试中0.1％样品失效时间(t0.1％)和50％样品失效时间(t50％)分别提高了18％和39％;32 MB静态随机存储器(SRAM)在正常工作电压和最小工作电压分别提高了9％和13％左右.     

第三代半导体SiC功率器件栅氧制备设备及工艺研究

第三代半导体碳化硅（SiC）材料具备耐高压、高频、高温等优越的特性,非常适合制作大功率电力电子器件。由于Si C材料不易氧化以及碳原子结构的影响,需更高温度进行SiO2/SiC生长,且氧化后SiO2/SiC界面存在大量的碳悬挂键,给器件的迁移率及可靠性等性能等带来影响,所以一般需要更高温度能力以及具备特殊后退火处理技术的工艺设备,以满足制备SiC高性能栅氧层的需求。本文重点介绍SiC MOSFET（金属氧化层半导体场效晶体管）器件栅氧制备的工艺特点,设备原理、以及工艺制备的效果。     

ISSG及其氮化工艺对栅氧化层性能的改善

栅氧化层的击穿和漏电是阻碍半导体集成电路发展的重要因素,提高栅氧化层的均匀性可极大地改善栅氧化层的性能。通过引入N2等惰性气体,在高温下对原位水汽氧化法形成的栅氧化层进行实时退火处理。实验结果表明:与没有经过高温N2实时退火处理的栅氧化层相比,经过高温N2实时退火处理的栅氧化层表面均匀度可提高40%左右,栅氧界面态总电荷可减少一个数量级。PMOS器件负偏压不稳定性(NBTI)测试中0.1%样品失效时间(t0.1%)和50%样品失效时间(t50%)分别提高28.6%和40.7%。     

前栅工艺下高k/金属栅CMOS器件EOT控制技术研究

随着CMOS器件特征尺寸的不断缩小,绝缘栅介质层也按照等比例缩小的原则变得越来越薄,由此而产生的栅漏电流增大和可靠性降低等问题变得越来越严重。传统的SiO2栅介质材料已不能满足CMOS器件进一步缩小的需要,而利用高介电常数栅介质(高k)取代SiO2已成为必然趋势。而在前栅工艺下,SiO2界面层生长问题严重制约了EOT的缩小以及器件性能的提升。介绍了一种前栅工艺下的高k/金属栅结构CMOS器件EOT控制技术,并成功验证了Al元素对SiO2界面层的氧吸除作用。     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

氮化H2-O2合成薄栅氧抗辐照特性

对氮化H2-O2合成薄栅氧抗辐照性能进行了研究,将H2-O2合成和氮氧化栅两种技术结合起来,充分利用两者的优点制成三层结构的Sandwich栅,对比常规氧化、H2-O2合成氧化和氮化H2-O2合成氧化三种方式及不同退火条件,得出氮化H2-O2合成氧化方法抗辐照性能最佳,采用硅化物工艺加快速热退火是未来抗辐照工艺发展的趋势;并对氮化H2-O2合成栅的抗辐照机理进行了研究.     

HfTiO氮化退火对MOS器件电特性的影响

采用磁控溅射方法,在Si衬底上淀积HfTiO高k介质,研究了NO、N2O、NH3和N2不同气体退火对MOS电特性的影响。结果表明,由于NO氮化退火能形成类SiO2/Si界面特性的HfTiSiON层,所制备的MOS器件表现出优良的电特性,即低的界面态密度、低的栅极漏电和高的可靠性。根据MOS器件栅介质(HfTiON/HfTiSiON)物理厚度变化(ΔTox)和电容等效厚度变化(ΔCET)与介质(HfTiON)介电常数的关系,求出在NO气氛中进行淀积后退火处理的HfTiON的介电常数达到28。     

氮化H_2-O_2合成薄栅氧抗辐照特性

对氮化 H2 - O2 合成薄栅氧抗辐照性能进行了研究 ,将 H2 - O2 合成和氮氧化栅两种技术结合起来 ,充分利用两者的优点制成三层结构的 Sandwich栅 ,对比常规氧化、H2 - O2 合成氧化和氮化 H2 - O2 合成氧化三种方式及不同退火条件 ,得出氮化 H2 - O2 合成氧化方法抗辐照性能最佳 ,采用硅化物工艺加快速热退火是未来抗辐照工艺发展的趋势 ;并对氮化 H2 - O2 合成栅的抗辐照机理进行了研究     

Nitrogen profile engineering in the interfacial SiON in a HfAlO/SiON gate dielectric by NO Re-oxidation

The effects of the nitrogen profile in the SiON-interfacial layer (IL) on the mobility in FETs employing a HfAlO/SiON gate dielectric have been investigated. In order to suppress the interdiffusion between HfAlO and SiON, the nitrogen concentration in SiON should be higher than 15 at%, while the substrate interface should be oxygen-rich in order to suppress the mobility reduction. By using an NO reoxidation of NH/sub 3/ formed 0.4-nm-thick silicon nitride, the mobility reduction due to the SiON-IL was successfully suppressed, and electron and hole mobility of 92% and 88% of those for SiO/sub 2/ at V/sub g/=1.1 V were obtained for HfAlO/SiON with equivalent oxide thickness (EOT) of 1.1 nm. By using nitrogen profile engineered SiON-IL, good equvalent oxide thickness (EOT) uniformity, low EOT, low gate leakage current, low defect density, and symmetrical threshold voltage were all achieved, indicating that a poly-Si/HfAlO/SiON gate stack would be a candidate as an alternative gate structure for low standby power FETs of half-pitch (hp)65 and hp45 technology nodes.     

Effects of the post nitridation anneal temperature on performances of the nano MOSFET with ultra-thin (<2.5 nm) plasma nitrided gate dielectric

A post nitridation annealing (PNA) is used to improve performances of the metal oxide semiconductor field effect transistor (MOSFETs) with nano scale channel and pulsed radio frequency decoupled plasma nitrided ultra-thin (<50 Å) gate dielectric. Effects of the PNA temperature on the gate leakage and the device performances are investigated in details. For a n-type MOSFET, as the PNA temperature rises from 1000 to 1050 °C, the saturation current and gate leakage are increased and reduced 7.9% and 3.81%, respectively. For a p-type MOSFET, the improvement is more significant i.e., 16.7% and 4.31% in saturation current increase and gate leakage reduction, respectively. The significant improvements in performance are attributed to the higher PNA temperature caused Si/SiON interface improvement and increase of EOT. Most of all, the high temperature PNA does not degrade the gate oxide integrity.     

Effect of fluorinated silicate glass passivation layer on electrical characteristics and dielectric reliabilities for the HfO2/SiON gate stacked nMOSFET

The superior characteristics of the fluorinated hafnium oxide/oxynitride (HfO₂/SiON) gate dielectric are investigated comprehensively. Fluorine is incorporated into the gate dielectric through fluorinated silicate glass (FSG) passivation layer to form fluorinated HfO₂/SiON dielectric. Fluorine incorporation has been proven to eliminate both bulk and interface trap densities due to Hf-F and Si-F bonds formation, which can strongly reduce trap generation as well as trap-assisted tunneling during subsequently constant voltage stress, and results in improved electrical characteristics and dielectric reliabilities. The results clearly indicate that the fluorinated HfO₂/SiON gate dielectric using FSG passivation layer becomes a feasible technology for future ultrathin gate dielectrics applications.     

Effect of Nitrogen Profile and Fluorine Incorporation on Negative-Bias Temperature Instability of Ultrathin Plasma-Nitrided SiON MOSFETs

The effects of plasma nitridation and fluorine incorporation on the components of negative-bias temperature instability (NBTI) in p-type MOSFETs with plasma-nitrided SiON gates were investigated. To clarify these effects, NBTI-induced threshold-voltage shift was separated into two components: one for generation of traps at the SiON/Si-substrate interface and one for positive charges within the SiON bulk. It was found that the proportions of the interface and bulk components can be controlled with the plasma nitridation method: The bulk component was increased by radio-frequency plasma nitridation, while the interface component was dominant in the case of electron-cyclotron-resonance plasma nitridation. Lowering the nitrogen concentration near the SiON/Si-substrate interface decreased the interface component. Lowering the nitrogen concentration near the poly-Si/SiON interface did not decrease NBTI, while it decreased positive oxide charges in the as-fabricated MOSFETs. Furthermore, it was demonstrated that the fluorine incorporation decreases the interface component in plasma-nitrided SiON gates, while it does not decrease the bulk component.     

Model to predict gate tunneling current of plasma oxynitrides

Two key parameters for silicon MOSFET scaling, equivalent oxide thickness (EOT) and gate leakage current density (J/sub g/) are measured and modeled for silicon oxynitride (Si-O-N) gate dielectrics formed by plasma nitridation of SiO/sub 2/. It is found that n-MOSFET inversion J/sub g/ is larger than p-MOSFET inversion J/sub g/ when the gate dielectric consists of less than 27% nitrogen atoms, indicating substrate injection of electrons is dominant for this range of plasma nitrided Si-O-N. To examine the intrinsic scaling of Si-O-N, we model EOT and n-MOSFET J/sub g/ for sub-2-nm physically thick gate dielectrics as a function of film physical thickness and nitrogen content. The model has four free fitting parameters and unlike existing models does not assume a priori the values of the oxide and nitride dielectric constant, barrier height, or effective mass. It indicates that at a given EOT, leakage current of n-MOSFETs with Si-O-N gate dielectrics reaches a minimum at a specific nitrogen content. Through the use of this model, we find that plasma nitrided Si-O-N can meet the 65-nm International Technology Roadmap for Semiconductors specifications for J/sub g/, and we estimate the nitrogen concentration required for each node and application.     

Recoiled-oxygen-free processing for 1.5 nm SiON gate-dielectric insub-100-nm CMOS technology

We have developed high-quality 1.5-nm-SiON gate dielectrics using recoiled-oxygen-free processing. We found that oxygen recoiling from a sacrificial oxide during ion implantation or defects induced by recoiled oxygen change the growth mechanism of SiON gate dielectrics of less than 2 nm and degrade the controllability of film thickness, film quality, and device electrical characteristics. PMOSFETs using the recoiled-oxygen-free process and As-implantation for the channel have better controllability of gate dielectric thickness, up to one-third less gate leakage current, a hundred times more reliable TDDB characteristics, and a 20% improvement in drain current compared to the conventional process. Thus, an Si substrate without recoiled oxygen is essential in forming high-quality SiON gate dielectrics of less than 1.5 nm. In addition, we will show that anneal before SiON gate dielectric formation removes the recoiled oxygen from the Si substrate and improves controllability of the gate SiON gate dielectric thickness     

ISSG及其氮化工艺对NBTI效应的改善

本文在对ISSG工艺特性简单分析的基础上讨论了ISSG氧化物薄膜的可靠性问题。讨论了ISSG工艺及其相关的氮化工艺对NBTI的改善原理。数据表明ISSG工艺及其相关的氮化工艺对NBTI效应有明显的改善作用。由于原子氧的强氧化作用,ISSG工艺中最终得到的氧化物薄膜体内缺陷少,界面态密度也比较小,氧化物薄膜的质量比较高。ISSG氮化工艺与传统炉管氧化物薄膜的氮化工艺的主要区别在于N所集中的位置不一样。ISSG工艺氮化是把等离子态的N^＋注入到多晶硅栅和SiQ2的界面,不会增加SiQ2和Si衬底的界面态,从而可以显著改善NBTI效应。而传统炉管氧化物薄膜的氮化是用NO或者N2O把N注入到SiQ2和Si衬底的界面,这样SiQ2和Si的界面态就会增加,从而增强NBTI效应。     

Transconductance in nitride-gate or oxynitride-gate transistors

Experimental evidence is presented to support the argument that border traps are responsible for the anomalous shape of the transconductance-gate voltage curve in MOS transistors with nitride of oxynitride gate dielectric when compared with their oxide counterpart. Our measurements have revealed a high density of border traps in the gate dielectric containing a high concentration of nitrogen. These border traps appear to affect the transconductance in two ways: in the low gate field region, the trapping of carriers causes a significant reduction of the carrier density and thus a reduced transconductance, while in the high gate field region the “screening” effect of trapped carriers causes a smoothening of the electronic interface, and thus an increased transconductance     

Recovery of negative bias temperature instability induced degradation of p-MOSFETs with SiON gate dielectric

This paper investigates the recovery property of p-MOSFETs with an ultra-thin SiON gate dielectric which are degraded by negative bias temperature instability (NBTI). The experimental results indicate that the recovery of the NBTI degradation occurs through an electrical neutralization of the NBTI-induced positive charges at the SiON/Si interface and in the gate dielectric. The neutralization of interface charges was a fast process occurring just after the device returned to the recovery state. The neutralization of positive charges in the gate dielectric was a slow process associated with the electron injection into the gate dielectric. Below the gate voltage for strong accumulation, the amount of recovery increased with an increase of the gate voltage. A further increase of gate voltage did not affect the amount of recovery. These experimental results indicate that the major cause of the recovery is a neutralization of the NBTI-induced positive charges by electrons instead of a hydrogen passivation of the NBTI-induced defect sites.     

Observation of nitrogen-enhanced doping deactivation at the polysilicon-oxynitride interface of pMOSFETs with 12-/spl Aring/ gate dielectrics

This letter reports the observation of a process integration issue that arises when large doses of nitrogen (>1/spl times/10/sup 15/ cm/sup -2/) are incorporated in oxynitride gate dielectric films targeting equivalent oxide thickness of 11-13 /spl Aring/. It is shown that capacitance-extracted active doping density at the polysilicon/oxynitride (poly/SiON) interface of boron-doped p/sup +/-polysilicon gated pMOSFETs decreases with increasing nitrogen dose of the oxynitride film as measured by X-ray photoelectron spectroscopy. A physical mechanism is proposed to explain experimental observations.