共查询到20条相似文献,搜索用时 15 毫秒
1.
Khan A.K. Magoshi H. Matsumoto T. Fujita J. Furuhashi M. Imai M. Kurose Y. Sato M. Sato K. Yamashita Y. Kinying Kwan Duc-Ngoc Le Yu J.H. Trung Nguyen Yang S. Tsou A. Chow K. Shen J. Min Li Jun Li Hong Zhao Yoshida K. 《Solid-State Circuits, IEEE Journal of》2001,36(11):1775-1784
A 150-MHz graphics rendering processor with an integrated 256-Mb embedded DRAM, delivering a rendering rate of 75 M polygons/s, is presented, 287.5 M transistors are integrated on a 21.3×21.7 mm 2 die in a 0.18-μm embedded DRAM CMOS process with six layers of metal. Design methodologies for hierarchical electrical and physical design of this very large-scale IC, including power distribution, fully hierarchical timing design, and verification utilizing a newly developed nonlinear model, clock design, propagation delay, and crosstalk noise management in multi-millimeter RC transmission lines, are presented 相似文献
2.
Kirihata T. Parries P. Hanson D.R. Hoki Kim Golz J. Fredeman G. Rajeevakumar R. Griesemer J. Robson N. Cestero A. Khan B.A. Geng Wang Wordeman M. Iyer S.S. 《Solid-State Circuits, IEEE Journal of》2005,40(6):1377-1387
An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time. A concurrent refresh scheduler utilizes up-count and down-count registers to identify at least one array to be refreshed at every clock cycle, emulating a classical distributed refresh mode. A command multiplier employs low frequency phased clock signals to generate the clock, commands, and addresses at rates up to 4/spl times/ that of the tester frequency. The macro integrates masked redundancy allocation logic during at speed multibank test. The hardware results show a 312-MHz random access frequency and 800-MHz multibank frequency at 1.2 V, respectively. 相似文献
3.
Aoki M. Etoh J. Itoh K. Kimura S. Kawamoto Y. 《Solid-State Circuits, IEEE Journal of》1989,24(5):1206-1212
Circuit techniques for 1.5-V CMOS DRAMS to be used in battery-based applications are presented. A three-level word pulse and a plate pulse are used to maintain the stored voltage in a memory cell, in spite of the minimized data-line voltage swing for reducing power dissipation. A 3.4- mu m/sup 2/ data-line shielded stacked capacitor (STC) cell is also proposed to enhance signal-to-noise ratio (SNR) in the memory cell array. The 1.5-V read/write operation is observed successfully through a 2-kbit test device. The data-holding time and alpha -particle-induced soft error rate of the device indicate that the possible performances for the 1.5-V DRAM are comparable to those for the existing 5-V DRAMs.<> 相似文献
4.
Multithreshold-voltage CMOS (MTCMOS) has a great advantage of lowering physical threshold voltages without increasing the power dissipation due to large subthreshold leakage currents. This paper presents the embedded SRAM techniques for high-speed low-power MTCMOS/SIMOX application-specified integrated circuits (ASICs) that are operated with a single battery cell of around 1 V. In order to increase SRAM operating frequency, a pseudo-two stage pipeline architecture is proposed. The address decoder using a pass-transistor-type NAND gate and a segmented power switch presents a short clocked wordline selection time. The large bitline delay in read operations is greatly shortened with a new memory cell using extra low-Vth nMOSs. The small readout signal from memory cells is detected with a high-speed MTCMOS sense amplifier, in which a pMOS bitline selector is merged. The wasted power dissipation in writing data is reduced to zero with a self-timed writing action. A 8 K-words×16-bits SRAM test chip, fabricated with a 0.35-μm MTCMOS/SIMOX process (shortened effective channel length of 0.17 μm is available), has demonstrated a 100-MHz operation under the worst power-supply condition of 1 V. At a typical 1.2 V, the power dissipation during the standby time is 0.2-μW and that of a 100-MHz operation with a checkerboard test pattern is 14 mW for single fan-in loads 相似文献
5.
Yokoyama Y. Itoh N. Hasegawa M. Katayama M. Akasaki H. Kaneda M. Ueda T. Tanaka Y. Yamasaki E. Todokoro M. Toriyama K. Miki H. Yagyu M. Takashima K. Kobayashi T. Miyaoka S. Tamba N. 《Solid-State Circuits, IEEE Journal of》2001,36(3):503-509
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns row-address-strobe access time and memory-cell area efficiency of 33% has been successfully developed with a single-side interface architecture, high-speed circuit design, and low-voltage design. In the high-speed circuit design, a multiword redundancy scheme and Y-select merged sense scheme are developed to achieve the performance goal. In the low-voltage design, a dual-complement charge-pump scheme and a decoupling capacitor utilizing a tantalum-oxide capacitor are developed to retain high performance at low supply voltage 相似文献
6.
Takahashi M. Nishikawa T. Hamada M. Takayanagi T. Arakida H. Machida N. Yamamoto H. Fujiyoshi T. Ohashi Y. Yamagishi O. Samata T. Asano A. Terazawa T. Ohmori K. Watanabe Y. Nakamura H. Minami S. Kuroda T. Furuyama T. 《Solid-State Circuits, IEEE Journal of》2000,35(11):1713-1721
A 240-mW single-chip MPEG-4 videophone LSI with a 16-Mb embedded DRAM is fabricated utilizing a 0.25-μm CMOS triple-well quad-metal technology. The videophone LSI is applied to the 3GPP 3G-324M video-telephony standard for IMT-2000, and implements the MPEG-4 video SPL1 codec, the AMR speech codec, and the ITU-T H.223 Annex B multiplexing/demultiplexing at the same time. Three 16-bit multimedia-extended RISC processors, dedicated hardware accelerators, and a 16-Mb embedded DRAM are integrated on a 10.84 mm×10.84 mm die. It also integrates camera, display, audio, and network interfaces required for a mobile video-phone terminal. In addition to conventional low-power techniques, such as clock gating and parallel operation, some new low-power techniques are also employed. These include an embedded DRAM with optimized configuration, a low-power motion estimator, and the adoption of the variable-threshold voltage CMOS (VT-CMOS). The MPEG-4 videophone LSI consumes 240 mW at 60 MHz, which is only 22% of that for a conventional multichip design. Variable threshold voltage CMOS reduces standby leakage current to 26 μA, which is only 17% of that for the conventional CMOS design 相似文献
7.
Wild A. Quigley J. Feddeler J. Ledford S. Caravella J. Shapiro F. Gilsdorf B. Hong M. Mietus D. Davies R.B. Parmar R. Jy-Der Tai Thomas J. Quarberg J. Hartung E. Sawan T. Carlquist J.H. Papworth K. Buxo J. Schriber M. Berens M. Warren D. Smith B. Mazuelos M. Bass K. Layton L. 《Solid-State Circuits, IEEE Journal of》1997,32(7):1049-1055
A 0.9-1.6-V, 1-MHz, 8-b microcontroller based on the 68HC08 architecture is presented. In addition to standard digital microcontroller functions, the chip features RAM, ROM, phase-locked loop (PLL) clock synthesis, and liquid crystal displays (LCD) drive capabilities operating from the voltage supply range of a single AA or AAA battery. The design used a library of CMOS microcontroller building blocks, converted into a low-voltage technology using unilateral transistors. The design approach was to optimize the conversion strategy for each functional block and to provide new designs when the conversion was insufficient. The chip exceeded specifications with blocks showing full functionality down to 0.7 V 相似文献
8.
Morishita F. Hayashi I. Matsuoka H. Takahashi K. Shigeta K. Gyohten T. Niiro M. Noda H. Okamoto M. Hachisuka A. Amo A. Shinkawata H. Kasaoka T. Dosaka K. Arimoto K. Fujishima K. Anami K. Yoshihara T. 《Solid-State Circuits, IEEE Journal of》2005,40(1):204-212
An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm/sup 2/ 16-Mb embedded DRAM macro is fabricated in 0.13 /spl mu/m logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36 % for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-/spl mu/W data retention power is realized by using the PDDR mode, which is 5% of conventional schemes. 相似文献
9.
Kim C. Kyung K.-H. Jeong W.-P. Kim J.-S. Moon B.-S. Chai J.-W. Yim S.-M. Choi J.-H. Han K.-H. Park C.-J. Hwang H.-S. Choi H. Cho S.-B. Portmann L. Cho S.-I. 《Solid-State Circuits, IEEE Journal of》1999,34(5):645-652
A 2.5-V, 72-Mbit DRAM based on packet protocol has been developed using (1) a rotated hierarchical I/O architecture to reduce power noise and to minimize the chip-size penalty associated with an 8-bit prefetch architecture implemented with 16 internal banks and 144 I/O lines, (2) a delay-locked-loop circuit using a high-speed and small-swing differential clock to achieve the peak bandwidth of 2.0 GByte/s in a single chip with low noise sensitivity, and (3) a flexible column redundancy scheme to efficiently increase redundancy coverage using a shifted I/O line scheme for multibank architecture 相似文献
10.
Guang-Kaai Dehng Ching-Yuan Yang June-Ming Hsu Shen-Iuan Liu 《Solid-State Circuits, IEEE Journal of》2000,35(8):1211-1214
A 900-MHz 1-V frequency synthesizer has been fabricated in a standard 0.35-μm CMOS technology. The frequency synthesizer consists of a divide-by-128/129 and 64/65 dual-modulus prescaler, phase-frequency detector, charge pump, and voltage-doubler circuit with an external voltage-controlled oscillator (VCO) and passive loop filter. The on-chip voltage-doubler circuit converts the 1-V supply voltage to the higher voltage which supplies the prescaler internally. In this way, the 900-MHz 1-V frequency synthesizer with an external VCO can be achieved. The measured phase noise is -112.7 dBc/Hz at a 100-kHz offset from the carrier, and the synthesizer dissipates 3.56 mW (not including VCOs) from a single 1-V supply when the switching frequency of the on-chip voltage doubler is 200 kHz and the power efficiency of the voltage doubler is 77.8%. The total chip area occupies 0.73 mm2 相似文献
11.
Taito Y. Tanizaki T. Kinoshita M. Igaue F. Fujino T. Arimoto K. 《Solid-State Circuits, IEEE Journal of》2003,38(11):1967-1973
This paper describes a 4-Mb embedded DRAM macro using novel fast random cycle architecture with sense-synchronized read/write (SSR/SSW). The test chip has been fabricated with a 0.15-/spl mu/m logic-based embedded DRAM process and the 1.5-V 143-MHz no-wait row random access operation has been confirmed. Data retention power is suppressed to 92 /spl mu/W owing to the hierarchical power supply and SSR. The macro size is 4.59 mm/sup 2/. The cell occupation ratio of the macro is 46%, which is the same as that of a conventional embedded DRAM macro. The macro size and the data retention power are 30% and 4.6%, respectively, of a 4-Mb embedded SRAM macro fabricated by an identical process. 相似文献
12.
A 2.7-V 900-MHz CMOS LNA and mixer 总被引:4,自引:0,他引:4
A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process 相似文献
13.
Dreibelbis J. Barth J. Kalter H. Kho R. 《Solid-State Circuits, IEEE Journal of》1998,33(11):1731-1740
A built-in self-test engine and test methodology have been developed for testing a family of high-bandwidth, high-density DRAM macros. The DRAM macros range in size from 256×16×128 to 2 K×16×256 (Word×Bit×Data) and are targeted for embedded applications in application-specific integrated circuit designs. The processor-based test engine, with two separate instruction storage memories, combines with flexible address, data, and clock generators to provide DRAM high-performance ac testing using a minimum of dedicated test pins. Test results are compressed through on-macro, two-dimensional, redundancy allocation logic to provide direct programming information for the fuser via a serial scan port. The design is intended for reuse on future DRAM-generation subarrays and can be adapted to any number of address or data-pin configurations 相似文献
14.
Horiguchi M. Aoki M. Tanaka H. Etoh J. Nakagome Y. Ikenaga S. Kawamoto Y. Itoh K. 《Solid-State Circuits, IEEE Journal of》1988,23(5):1128-1132
A dual-operating-voltage scheme (5 V for peripheral circuits and 3.3 V for the memory array) is shown to be the best approach for a single 5-V 16-Mb DRAM (dynamic random-access memory). This is because the conventional scaling rule cannot apply to DRAM design due to the inherent DRAM word-line boosting feature. A novel internal voltage generator to realize this approach is presented. Its features are the switching of two reference voltages, a driver using a PMOS-load differential amplifier, and the word-line boost based on the regulated voltage, which can ensure a wider memory margin than conventional circuits. This approach is applied to an experimental 16-Mb DRAM. A 0.5% supply-voltage dependency and 30-ns recovery time are achieved 相似文献
15.
A new architecture for phase-locked loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5-μm CMOS process, a fully integrated fractional-N synthesizer prototype with a third-order sigma-delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is, 0.9 × 1.1 mm2. The settling time is less than 100 μs and the phase noise is -118 dBc/Hz at 600-kHz offset 相似文献
16.
《Vehicular Technology, IEEE Transactions on》1977,26(1):76-81
The system concepts for a high capacity personal radio telephone system are described. Previous systems for mobile radio telephone service have been based on a rigid assignment of frequencies to specific small geographic areas within the total coverage area. This approach has led to conservative geographic frequency reuse constraints and the requirement for accurate location techniques in the system. Through the utilization of the power imbalance that exists in the proposed portable radio telephone system between base and portable unit transmitters these constraints are eliminated. It will be shown how this power imbalance allows the selection of the optimum signal for the portable unit and relaxed requirements on location and reuse of frequencies. The required signal-to-interference ratios must be obtained within a design reliability level over the coverage area. Computer simulation of the frequency reuse plan and the propagation variability over the area indicates the nominal repeat intervals necessary as a function of this reliability level. A reuse plan that obtains the required repeat intervals with a high degree of spectral efficiency, through the combined use of geographic and frequency separation, will be presented. This system called tertiary offset, achieves a significant increase in interference protection by splitting each channel into a group of three channels and utilizing each subgroup in a different pattern of reuse over the area. The improvement due to this plan will be shown. 相似文献
17.
Dosaka K. Konishi Y. Hayano K. Himukashi K. Yamazaki A. Iwamoto H. Kumanoya M. Hamano H. Yoshihara T. 《Solid-State Circuits, IEEE Journal of》1992,27(11):1534-1539
A 4-Mb cache dynamic random access memory (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, is described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7-μm CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm2 is only a 7% increase over the conventional 4-Mb DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity 相似文献
18.
A 2-V 10.7-MHz CMOS limiting amplifier/RSSI 总被引:2,自引:0,他引:2
Po-Chiun Huang Yi-Huei Chen Chorng-Kuang Wang 《Solid-State Circuits, IEEE Journal of》2000,35(10):1474-1480
This paper presents low-voltage low-power CMOS circuit design techniques for an intermediate frequency (IF) limiting amplifier and received signal strength indicator (RSSI). The architecture of the limiting amplifier and RSSI employed is determined by the optimal power consumption for a specified speed, overall gain, and accuracy. Each gain cell of the limiting amplifier employs folded diode load for low-voltage operation. Offset is reduced by a cross-connected source-coupled pair offset subtractor that is along the signal path. Full-wave current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low voltage and low power. Using a single 2-V supply voltage, measured results demonstrate the input dynamic range is larger than 75 dB for 10.7-MHz IF application. The prototype occupies an active area of 0.4 mm2 using a 0.6-μm digital CMOS technology. The power dissipation is 6.2 mW 相似文献
19.
《Circuits and Systems II: Express Briefs, IEEE Transactions on》2009,56(11):805-809
20.
Arimoto K. Matsuda Y. Furutani K. Tsukude M. Ooishi T. Mashiko K. Fujishima K. 《Solid-State Circuits, IEEE Journal of》1990,25(1):11-17
An array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. Based on a new access model, the combination of a hierarchical data bus configuration and multipurpose register (MPR) provides high-speed array access. The MPR also includes practical array-embedded error checking and correcting (ECC) with little area penalty and no access overhead in the page mode. The array architecture is applied to a scaled-down 16-Mb DRAM and has achieved high performance 相似文献