可编程SoC前程似锦

由于SoC能提供更好的性能、更低的功耗、更小的印制电路板空间和更低的成本,在半导体业界被视为继微处理器之后的第二大热门产品。     

可编程逻辑器件产业发展趋势

可编程逻辑器(PLD)是70年代发展起来的新型逻辑器件,可以完全由用户配置以完成某种特定的逻辑功能。经过80年代的发展,PLD行业初步形成,而进入90年代以后,可编程逻辑器件成为半导体领域中发展最快的产品之一。可编程器件是在ASIC设计的基础上发展起来的,在ASIC设计方法中,通常采用全定制和半定制电路设计方法,但设计完成后如果不能满足要求,还要重新设计再进行验证。这样不但会导致设计开发周期变长,产品上市时间难以保证,而且会大大增加产品的开发费用。     

在线可编程—高密度PLD技术的核心

一、什么是高密度PLD器件 高密度PLD器件是相对于传统简单PLD(PAL/GAL)而言的,一般指引脚数在44条以上且集成度在1000门以上,并设有可编程互连资源和可编程逻辑块的用户现场可编程的可编程逻辑器件,是通常所说的可编程门阵列(FPGA)和复杂PLD(CPLD)的总称。 复杂PLD是乘积项阵列的集合,其逻辑单元与输入输出单元的连接关系是比较固定的,各个PAL块可以通过共享的可编程互连资源     

SoC新技术--可编程逻辑IP核

随着半导体技术的飞速发展,单个硅片上的集成度越来越高,SoC(System-On-a-Chip）已成为IC(Integrated Circuit）设计技术的主流。由于市场竞争的日益激烈,TTM(Time to Market）已成为一个非常重要的因素,直接影响到产品的市场份额和开发商的利润。如何更快、更有效的完成SoC设计逐渐成为人们关注的焦点。可编程逻辑IP核技术的出现有效的缩短了SoC的设计周期并使得芯片设计更具灵活性。本文将对这种技术进行详细的介绍。     

SOPC（片上可编程系统）：灵活、高效的解决之道

SOPC(System on a programmable chip:片上可编程系统)是Altera公司提出来的一种灵活、高效的解决方案,它将处理器、存储器、I/O口、LVDS、CDR等系统设计需要的东西集成到一个PLD器件上,构建成一个可编程的片上系统,它所具有的灵活性、低成本可让系统设计者获益非浅。 11月1日,Altera公司在北京举行了半天的研讨会,主要讨论了SOPC蕴含的技术,并展示了实践中构建的基于SOPC的系统。借这次会议机会,我采访了Altera公司中国区总经理赵典锋先生,请他详细介绍了SOPC的关键技术和应     

MCS-51单片机与PLD可编程器件接口设计

采用Lattice公司的PLD器件ISPLSI1032。基于VHDL描述语言设计了一种MCS-51单片机与PLD可编程逻辑器件的接口电路,该接口电路具有体积小,性能可靠,开发便捷,所需外围元件少等优点。     

可编程器件PLD的动态配置

本文以Altera公司的CPLD器件为例，通过比较可编程器件的各种配置方式，分析了被动并行异步模式（PPA）在完成动态配置方面的优势，及其提高了系统性能的有效性。     

应用VHDL语言在PLD器件上设计实现可编程计数器

研究用VHDL语言采用TOP TO DOWN设计方法实现了一种可以完成二进制、十进制、可逆计数功能的可编程计数器；采用MAX＋PLUSII集成开发环境编辑、综合、仿真，并下载到PLD器件中，经仿真和实际电路测试，该计数器性能可靠。     

流量管理SoC设计者越来越大的梦魇

SoC（系统级芯片）在先于它出现的板级计算机上开始了自己的生命;作为一个中央处理器,其CPU总线连接到本地内存与外设控制器。从此以后,这种以CPU为中心、面向总线的架构一直是很多SoC的优先规划。     

SoCs security: a war against side-channels

This article presents the state-of-the-art of the physical security of smart devices. Electronic devices are getting ubiquitous and autonomous: their security is thus becoming a predominant feature. Attacks targeting the physical layer are all the more serious as hardware is not naturally protected against them. The attacks typically consist in either tampering with the device so as to make it malfunction or in spying at some information it leaks. Those attacks, either active or passive, belong to the side-channel attack class. Active attacks operate by writing on an ad hoc side-channel: a degree a freedom normally not available to the end-user is modified by force. Passive attacks consist in listening to a side-channel: the attacker is thus able to gain more information about the device operation than it is supposed to. Counter-measures against both types of attacks have been proposed and we show that only some of them are relevant. Active attacks are forfeited by an appropriate detection mechanism and passive attacks by the removal of all sorts of information leakage. As a consequence, securing hardware consists in watching side-channels or removing them if possible. The increase of security is mainly driven by two trends: integration of the system (on a SoC) for improved discretion and development of a dedicated symptom-free electroniccad. SoCs security is thus foreseen to become a discipline in itself.     

Wafer-Level Modular Testing of Core-Based SoCs

Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of core-based system-on-chip (SoC) designs. Packaging has been recognized as a significant contributor to the product cost for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort) is used in the semiconductor industry to screen defective dies. However, since test time is a major practical constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can be applied to the die under test. We present an optimal test-length selection technique for wafer-level testing of core-based SoCs. This technique, which is based on a combination of statistical yield modeling and integer linear programming, allows us to determine the number of patterns to use for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. We also present a heuristic method to handle large next-generation SoC designs. Simulation results are presented for five of the ITC'02 SoC Test benchmarks, and the optimal test-length selection approach is compared with the heuristic method.     

Power and Reliability Management of SoCs

Today's embedded systems integrate multiple IP cores for processing, communication, and sensing on a single die as systems-on-chip (SoCs). Aggressive transistor scaling, decreased voltage margins and increased processor power and temperature have made reliability assessment a much more significant issue. Although reliability of devices and interconnect has been broadly studied, in this work, we study a tradeoff between reliability and power consumption for component-based SoC designs. We specifically focus on hard error rates as they cause a device to permanently stop operating. We also present a joint reliability and power management optimization problem whose solution is an optimal management policy. When careful joint policy optimization is performed, we obtain a significant improvement in energy consumption (40%) in tandem with meeting a reliability constraint for all SoC operating temperatures     

用可编程逻辑器件实现专用数字集成电路的功能设计

以计算机科学和微电子技术为先导的 EDA技术已成为电子设计领域的一个新技术 ,它的高速发展为电子系统和集成电路的设计带来了一场革命。本文用具体的例子说明了用 EDA软件开发平台将可编程逻辑器件设计为专用数字集成电路的具体方法。     

Robust Concurrent Online Testing of Network-on-Chip-Based SoCs

Lifetime concerns for complex systems-on-a-chip (SoC) designs due to decreasing levels in reliability motivate the development of solutions to ensure reliable operation. A precursor to any proposed recovery scheme would require the identification of failures in the system. Non-concurrent in-field testing is an impractical solution due to prohibitive costs in terms of test power and test time. This novel research proposes the use of concurrent online testing (COLT) to circumvent these issues. A test infrastructure-intellectual property (TI-IP) is deployed within network-on-chip (NoC)-based SoC designs to provide online test support while managing intrusion of test into executing applications within the system. This research describes the architecture and operation of a TI-IP capable of COLT. To address scalability of this solution, we show how these would operate when more than one is deployed in an SoC. In the absence of benchmarks for the analysis of COLT, two baseline and eight TI-IP configuration variations within SoC test configurations were developed using application and test benchmarks from the research domain. The power profiles from the NoCSim simulation environment are reported here demonstrating how different configurations of TI-IPs would operate. A robust TI-IP protocol is also specified and possible hazards and their mitigations are identified.      

GALDS: a complete framework for designing multiclock ASICs and SoCs

A Globally Asynchronous, Locally Synchronous (GALS) system with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimal power consumption. With the mechanism for implementing dynamic voltage scaling at each synchronous domain left up to the designer, our Globally Asynchronous, Locally Dynamic System (GALDS) provides a top-down, system-level means to maximize power reduction in an integrated circuit and facilitate system-on-a-chip (SoC) design. Our solution includes three distinct components: a novel bidirectional asynchronous FIFO to communicate between independently clocked synchronous blocks , an all-digital dynamic clock generator to quickly and glitchlessly switch between frequencies and a digitally controlled oscillator to generate the global fixed frequency clocks required by the all-digital dynamic clock generator. In addition to being capable of reducing power consumption when combined with dynamic voltage scaling, a GALDS design benefits from numerous other advantages such as simplified clock distribution, high performance operation and faster time-to-market through the modular nature of the architecture.     

用ABEL软件开发PLD器件

ＡＢＥＬ软件是一个很好的ＰＬＤ开发软件，用它可以方便地描述各种硬件逻辑，实现ＰＬＤ器件的设计。本文作者在工作实践当中，多次使用ＡＢＥＬ软件设计了一些ＰＬＤ器件，总结了一些经验，供大家参考。     

电源SoC:或许是好用的“疯狂”创意

对于电源管理IC,把包括开关、控制和无源元件在内的整个电源安装在一块芯片上,就能促成更高的功率效率,并降低散热量。尖端的电源拓扑结构、微型磁性元件、更快的开关器件可以共同使单片电源成为现实。