0.1 μm Schottky-collector AlAs/GaAs resonant tunneling diodes

The Schottky-collector resonant tunneling diode (RTD) is an RTD with the normal N+ collector and ohmic contact replaced by a Schottky contact, thereby eliminating the associated parasitic resistance. With submicron Schottky contact dimensions, the remaining components of the parasitic series resistance can be greatly reduced, resulting in an increased maximum frequency of oscillation, f_max. AlAs/GaAs Schottky-collector RTDs were fabricated using 0.1 μm T-gate technology developed for high electron mobility transistors. From their measured dc and microwave parameters, and including the effect of the quantum well lifetime, f_max=900 GHz is computed     

Design considerations for planar Schottky barrier diodes

The cut-off frequency of the simplest planar Schottky diode on a uniformly doped n-layer of GaAs is derived. The theoretical results are given as functions of doping concentration and layer thickness with the specific contact resistance as parameter. An improved planar diode structure is presented with several short Schottky contact fingers connected in parallel. Experimental values ranging from 100 to 300 GHz agree with the calculated values when parasitic capacitances are taken into account.     

Submicron transferred-substrate heterojunction bipolar transistors

We report submicron transferred-substrate AlInAs/GaInAs heterojunction bipolar transistors (HBT's). Devices with 0.4-μm emitter and 0.4-μm collector widths have 17.5 dB unilateral gain at 110 GHz. Extrapolating at -20 dB/decade, the power gain cutoff frequency f_max is 820 GHz. The high f_max, results from the scaling of HBT's junction widths, from elimination of collector series resistance through the use of a Schottky collector contact, and from partial screening of the collector-base capacitance by the collector space charge     

Experimental and numerical analysis of channel-length-dependent electrical properties in bottom-gate,bottom-contact organic thin-film transistors with Schottky contact

Channel length dependence of field-effect mobility and source/drain parasitic resistance in pentacene thin-film transistors with a bottom-gate, bottom-contact configuration was investigated. Schottky barrier effect such as nonlinear behaviors in transistor output characteristics appeared and became more prominent for shorter channel length less than 10 μm, raising some concerns for a simple utilization of conventional parameter extraction methods. Therefore the gate-voltage-dependent hole mobility and the source/drain parasitic resistance in the pentacene transistors were evaluated with the aid of device simulation accounting for Schottky contact with a thermionic field emission model. The hole mobility in the channel region shows smaller values with shorter channel length even after removing the influence of Schottky barrier, suggesting that some disordered semiconductor layers with low carrier mobility exist near the contact electrode. This experimental data analysis with the simulation enables us to discuss and understand in detail the operation mechanism of bottom-gate, bottom-contact transistors by considering properly each process of charge carrier injection, carrier flow near the contact region, and actual channel transport.     

Advanced model and analysis of series resistance for CMOS scalinginto nanometer regime. II. Quantitative analysis

Source/drain (S/D) series resistance components and device/process parameters contributing to series resistance are extensively analyzed using advanced model for future CMOS design and technology scaling into the nanometer regime. The total series resistance of a device is found to be very sensitive to the variations of the sidewall thickness, the doping concentration in the deep junction region, and the Schottky barrier height of the silicide contact. A prediction of series resistance trends with technology generation indicates that silicide-diffusion contact resistance and overlap resistance will be major components in the total series resistance of nanometer-scale CMOS transistors scaled according to the ITRS roadmap. The key factors for challenging scaling barriers related to parasitic resistance are quantitatively examined as a function of technology scaling and it is shown that the series resistance can be substantially reduced through controlling both the abruptness of the S/D junction profile and the silicide Schottky barrier engineering     

AlGaAs/GaAs heterojunction bipolar transistors with small size fabricated by a multiple self-alignment process using one mask

A multiple self-alignment process for HBT's using one mask is developed to form emitters, emitter contacts, emitter contact leads, buried small collectors, base contacts, and base contact leads. This process makes it possible to produce HBT's of very small size and to reduce parasitic elements. An AlGaAs/GaAs HBT fabricated by the process, with an emitter 1 × 20/µm²in size and a buried collector by O⁺implantation gives a good performance of ft= 54 GHz and fmax= 42 GHz. The performance may be explained by the reduction of parasitic elements, base transit time, and collector depletion layer transit time.     

Device performance improvement of InGaP/InGaAs doped-channel FETs

Partial drain/source ohmic recess InGaP/InGaAs/GaAs doped-channel field-effect transistors (OR-DCFETs) are proposed and fabricated in this study. The proposed ohmic recess process reduces the parasitic ohmic alloyed resistance caused by the undoped Schottky layer and therefore improves the device performance in terms of dc and source resistance, as well as RF characteristics. We compare the proposed devices with the DCFETs using the conventional process by means of experiments, where the Yang-Long method is used to analyze the effect of parasitic source resistances.     

Optimum doping profile for minimum ohmic resistance and high-breakdown voltage

The optimum doping profile of a lightly doped layer that introduces the minimum series resistance and sustains a given junction breakdown voltage is derived. The theory applies to a one-dimensional Schottky diode and qualitatively to the collector or drain doping profiles of transistors. The minimum series resistance is found to be about 3.7 × 10^-9Vmin{B}max{2.6}Ω.cm²for an n silicon layer. The optimum doping profile can be closely approximated by a conventional uniformly doped n-n⁺structure.     

Physical equivalent circuit model for planar Schottky varactordiode

A physical equivalent circuit model for the planar GaAs Schottky varactor diode is presented. The model takes into account the distributed resistance and capacitance of the active layer, the sidewall capacitance, and the parasitic resistances and accurately accounts for the high series resistance observed near the pinch-off voltage. The dependence of the maximum series resistance on varactor size, frequency, and doping profile has been theoretically investigated, and the results agree well with experimental data. The proposed model can be easily used for optimization of planar Schottky varactor diodes with regard to broadband monolithic VCO constraints     

高温正向栅电流下Ti/Pt/Au栅SiC MESFET的栅退化机理

SiC MESFET器件的性能强烈依赖于栅肖特基结的特性,而栅肖特基接触的稳定性直接影响其可靠性.针对SiC MESFET器件在微波频率的应用中射频过驱动导致高栅电流密度的现象,设计了两种栅极大电流的条件,观察栅肖特基接触和器件特性的变化,并通过对试验数据的分析,确定了栅的寄生并联电阻的缓慢退化是导致栅肖特基结和器件特性退化,甚至器件烧毁失效的主要原因.     

Size dependence of the magnetic and electrical properties of thespin-valve transistor

The electrical and magnetic properties of the spin-valve transistor (SVT) are investigated as a function of transistor size. A new fabrication process, designed to study the size dependence of the SVT properties, uses: silicon-on-insulator (SOI) wafers, a combination of ion beam and wet etching and a negative tone photoresist (SU8) as an insulating layer. The Si/Pt emitter and Si/Au collector Schottky barrier height do not depend on the transistor dimensions. The parasitic leakage current of the Si/Au collector is, however, proportional to its area. The relative collector current change with magnetic field is 240%, independent of size, while the transfer ratio starts to decrease for SVTs with an emitter area below 25 × 25 μm². The maximum input current is found to be limited by the maximum current density allowed in the base (1.7 × 10⁷ A/cm²), which is in agreement with the maximum current density for spin valves     

Modeling the gate bias dependence of contact resistance in staggered polycrystalline organic thin film transistors

We have modeled the dependence on the gate voltage of the bulk contact resistance and interface contact resistance in staggered polycrystalline organic thin film transistors. In the specific, we have investigated how traps, at the grain boundaries of an organic semiconductor thin film layer placed between the metal electrode and the active layer, can contribute to the bulk contact resistance. In order to the take into account this contribution, within the frame of the grain boundary trapping model (GBTM), a model of the energy barrier E_B, which emerges between the accumulation layer at the organic semiconductor/insulator interface and injecting contact, has been proposed. Moreover, the lowering of the energy barrier at the contacts interface region has been included by considering the influence of the electric field generated by the accumulation layer on the injection of carriers at the source and on the collection of charges from the accumulation layer to the drain contact. This work outlines both a Schottky barrier lowering, determined by the accumulation layer opposite the source electrode, as well as a Poole-Frenkel mechanism determined by the electric field of the accumulation layer active at the drain contact region. Finally it is provided and tested an analytical equation of our model for the contact resistance, summarizing the Poole-Frenkel and Schottky barrier lowering contribution with the grain boundary trapping model.     

A high cutoff frequency planar Schottky diode with a stripe geometry junction

Design and experimental results of a planar Schottky-barrier diode suitable for use in MIC's are presented. The Schottky junction has a stripe geometry with a closely located ohmic contact. This geometry is effective in reducing the skin-effect parasitic resistance to yield a high cutoff frequency. The experimental diode has been fabricated using n and n⁺GaAs layers selectively grown on a semi-insulating substrate. A zero-bias cutoff frequency of more than 700 GHz has been obtained.     

Epitaxial V-groove bipolar integrated circuit process

A new four-mask "V-groove" process for the fabrication of bipolar integrated circuits has been developed. The process utilizes epitaxial ν/n⁺/n^-layers and anisotropic etching oflangle100ranglesilicon to eliminate the buried layer and isolation diffusions as well as the need for masking the base diffusion of the standard six-mask bipolar integrated circuit process, n-p-n transistor, resistor, and Schottky diode characteristics are equivalent to or exceed those of the standard process. A five-mask V-groove process provides improved lateral p-n-p transistors compared with the four-mask approach. The V-groove integrated circuit structure offers simpler processing, smaller isolation capacitances, lower parasitic collector resistances, larger packing densities, and higher junction breakdown voltages than standard bipolar integrated circuits without degradation of other properties.     

The ohmic contact formation mechanism of Au/Pt/Pd ohmic contact to p-ZnTe

The ohmic contact formation mechanism and the role of Pt layer of Au(500Å) Pt(500Å)/Pd(100Å) ohmic contact to p-ZnTe were investigated. The specific contact resistance of Au/Pt/Pd contact depended strongly on the annealing temperature. As the annealing temperature increased, the specific contact resistance decreased and reached a minimum value of 6×10^?6 Θcm² at 200°C. From the Hall measurement, the hole concentration increased with the annealing temperature and reached a maximum value of 2.3×10¹⁹ cm^?3 at 300°C. The Schottky barrier height decreased with the increase of annealing temperature and reached a minimum value of 0.34 eV at 200°C and it was due to the interfacial reaction of Pd and ZnTe. Therefore, the decrease of contact resistance was due to the increase of doping concentration as well as the decrease of Schottky barrier height by the interfacial reaction of Pd ZnTe. The specific contact resistances of Au Pd, Au/Pt/Pd and Au/Mo/Pd as a function of annealing time was investigated to clarify the role of Pt layer.     

A new epitaxial lateral overgrowth silicon bipolar transistor

A new device structure and method of fabricating a silicon bipolar transistor is proposed. The device has reduced collector parasitic capacitance and resistance as compared to other advanced bipolar technologies. By using selective and lateral epitaxial overgrowth techniques the buried (N+) layer is not necessary. Two-dimensional computer simulations show theC_{CS} times R_{C}product to be reduced by a factor of 5.45 along with reduced CCB.     

New collector undercut technique using a SiN sidewall for low basecontact resistance in InP/InGaAs SHBTs

A new collector undercut process using SiN protection sidewall has been developed for high speed InP/InGaAs single heterojunction bipolar transistors (HBTs). The HBTs fabricated using the technique have a larger base contact area, resulting in a smaller DC current gain and smaller base contact resistance than HBTs fabricated using a conventional undercut process while maintaining low C_bc. Due to the reduced base contact resistance, the maximum oscillation frequency (f_max) has been enhanced from 162 GHz to 208 GHz. This result clearly shows the effectiveness of this technique for high-speed HBT process, especially for the HBTs with a thick collector layer, and narrow base metal width     

Direct measurements of interfacial contact resistance, end contact resistance, and interfacial contact layer uniformity

A four-terminal microelectronic test structure and test method are described for electrically determining the degree of uniformity of the interfacial layer in metal-semiconductor contacts and for directly measuring the interfacial contact resistance. A two-dimensional resistor network model is used to obtain the relationship between the specific contact resistance and the measured interfacial contact resistance for contacts with a uniform interfacial layer. A new six-terminal test structure is used for the direct measurement of end contact resistance and the subsequent determination of front contact resistance. A methodology is described for reducing the effects of both contact-window mask misalignment and parasitic resistance associated with these measurements. Measurement results are given for 98.5-percent Al/1.5- percent Si and 100-percent Al contacts on n-type silicon.     

Monolithic Schottky-collector resonant tunnel diode oscillatorarrays to 650 GHz

We report monolithic array oscillators incorporating Schottky-collector resonant tunnel diodes (SRTD's). In the SRTD, a 0.1-μm width Schottky collector contact provides a greatly reduced device series resistance, resulting in an estimated 2.2 THz maximum frequency of oscillation. A 64-element oscillator array oscillated at 650 GHz while a 16-element array produced 28 μW at 290 GHz     

Measurement of collector and emitter resistances in bipolartransistors

New DC methods to measure the collector resistance R_C and emitter resistance R_E are presented. These methods are based on monitoring the substrate current of the parasitic vertical p-n-p transistor linked with the n-p-n intrinsic transistor. The p-n-p transistor is operated with either the bottom substrate-collector or the top base-collector p-n junction forward-biased. This allows for a separation of the various components of R_C. R_E is obtained from the measured lateral portion of R_C and the collector-emitter saturation voltage. Examples of measurements on advanced self-aligned transistors with polysilicon contacts are shown. The results show a very strong dependence of R_C on the base-emitter and base-collector voltages of the n-p-n transistor. The bias dependence of R_C is due to the conductivity modulation of the epitaxial collector. From the measured emitter resistance R_E a value for the specific contact resistance for the polysilicon emitter contact of ρ_c≅50 Ω-μm² is obtained