Wafer temperature measurement in a rapid thermal processor with modulated lamp power

Pyrometry methods utilizing modulated lamp power (“ripple”) were used to improve wafer temperature measurement and control in rapid thermal processing (RTP) for silicon integrated circuit production. Data from a manufacturing line where ripple pyrometers have been tested show significantly reduced wafer to wafer and lot to lot variations in final test electrical measurements and increased yields of good chips per wafer. The pyrometers, an outgrowth of Accufiber’s ripple technique, are used to compensate for ordinary production variations in the emissivities of the backsides of wafers, which face the pyrometers. Power to the heating lamps is modulated with oscillatory functions of time at either the power line frequency or under software control. Fluctuating and quasi-steady components in detected radiation are analyzed to suppress background reflections from the lamps and to correct for effective wafer emissivity. Sheet resistances of annealed wafers with high dose shallow As implants were used to infer temperature measurement capability over a range in backside emissivity. Emissivities are varied when depositing or growing one or more layers of silicon dioxide, silicon nitride, or polycrystalline silicon on the backsides of the wafers.     

Rapid thermal processing of silicon wafers with emissivity patterns

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.     

Using wavelength-dependent emissivity of semiconductor wafer tomodel heat transfer in rapid thermal processing station

This paper develops an approach for using a wavelength-dependent emissivity model of a semiconductor wafer in calculating heat transfer in a rapid thermal processing (RTP) station. The wafer emissivity is modeled by a generalized polynomial in wavelength where the coefficients may be functions of temperature. A comparison of experimental data with simulated results for a silicon wafer is provided     

Temperature measurement in rapid thermal processing using theacoustic temperature sensor

Acoustic techniques are used to monitor the temperature of silicon wafers in rapid thermal processing environments from room temperature to 1000°C with ±5°C accuracy. Acoustic transducers are mounted at the bases of the quartz pins that support the silicon wafer during processing. An electrical pulse applied across the transducer generates an extensional mode acoustic wave which is guided by the quartz pins. The extensional mode is converted into Lamb waves (a guided plate mode) in the silicon wafer which acts as a plate waveguide. The Lamb wave propagates across the length of the silicon wafer and is converted back into an extensional mode at the other pin. The extensional mode acoustic wave is detected and the total time of flight is obtained. The time of flight of the extensional mode in the quartz pin is measured using pulse echo techniques and is subtracted from the total time of flight. Because the velocity of Lamb waves in the silicon wafer is systematically affected by temperature, the measurement of the time of flight of the Lamb wave provides the accurate temperature of the silicon wafer. The current implementation provides a ±5°C accuracy at 20 Hz data rate. Further improvements in electronics and acoustics should enable ±1°C measurements. The acoustic temperature sensor (ATS) has several advantages over conventional temperature measurement techniques. Unlike pyrometric measurements, ATS measurements are independent of emissivity of the silicon wafer and will operate down to room temperature. ATS also does not have the contact and contamination problems associated with thermocouples     

Thermal and stress analysis of semiconductor wafers in a rapidthermal processing oven

Results are presented from studies of heat transfer in a rapid thermal processing (RTP)-type oven used for several semiconductor wafer processes. These processes include: (1) rapid thermal annealing; (2) thermal gradient zone melting; and (3) lateral epitaxial growth over oxide. The heat transfer studies include the measurement of convective heat transfer in a similar apparatus, and the development of a numerical model that incorporates radiative and convective heat transfer. Thermal stresses that are induced in silicon wafers are calculated and compared to the yield stress of silicon at the appropriate temperature and strain rate. Some methods for improving the temperature uniformity and reducing thermal stresses in the wafers are discussed     

Recent developments in rapid thermal processing

Rapid thermal annealing (RTA) with a short dwell time at maximum temperature is used with ion implantation to form shallow junctions and polycrystalline-Si gate electrodes in complementary, metal-oxide semiconductor (CMOS) Si processing. Wafers are heated by electric lamps or steady heat sources with rapid wafer transfer. Advanced methods use “spike anneals,” wherein high-temperature ramp rates are used for both heating and cooling while also minimizing the dwell time at peak temperature to nominally zero. The fast thermal cycles are required to reduce the undesirable effects of transient-enhanced diffusion (TED) and thermal deactivation of the dopants. Because junction profiles are sensitive to annealing temperature, the challenge in spike annealing is to maintain temperature uniformity across the wafer and repeatability from wafer to wafer. Multiple lamp systems use arrayed temperature sensors for individual control zones. Other methods rely on process chambers that are designed for uniform wafer heating. Generally, sophisticated techniques for accurate temperature measurement and control by emissivity-compensated infrared pyrometry are required because processed Si wafers exhibit appreciable variation in emissivity.     

Thermal uniformity of 12-in silicon wafer during rapid thermalprocessing by inverse heat transfer method

Through an inverse heat transfer method, this paper presents a finite difference formulation for determination of incident heat fluxes to achieve thermal uniformity in a 12-in silicon wafer during rapid thermal processing. A one-dimensional thermal model and temperature-dependent thermal properties of a silicon wafer are adopted in this study. Our results show that the thermal nonuniformity can he reduced considerably if the incident heat fluxes on the wafer are dynamically controlled according to the inverse-method results. An effect of successive temperature measurement errors on thermal uniformity is discussed. The resulting maximum temperature differences are only 0.618, 0.776, 0.981, and 0.326°C for 4-, 6-, 8- and 12-in wafers, respectively. The required edge heating compensation ratio for thermal uniformity in 4-, 6-, 8and 12-in silicon wafers is also evaluated     

Radiation thermometry of silicon wafers in a diffusion furnace forfabrication of LSI

A radiation thermometry technique suitable for measuring the temperature of silicon wafers in a diffusion furnace has been developed. A principal feature of this technique is that it measures the temperature of wafers that are not in the line of sight of a conventional pyrometer. An optical guide, consisting of two quartz prisms, gives optical access to interior wafers in the load. A measuring wavelength of 0.9 μm is selected since a silicon wafer is opaque and its emissivity does not depend on temperature at this wavelength. The accuracy of the thermometry is examined by comparing the measured value of the pyrometer with that of a thermocouple. The two measured values agree within ±2°C in a steady state. When wafers are being inserted into or drawn out from the furnace, however, an error is caused by the veiling glare at the optical guide and the wafer     

Transient thermal analysis of sapphire wafers subjected to thermal shocks

Rapid heating and cooling are commonly encountered events in integrated circuit processing, which produce thermal shocks and consequent thermal stresses in wafers. The present paper studies the heat transfer in sapphire wafers during a thermal shock as well as the dependence of the wafer temperature on various process parameters. A three-dimensional finite-element model of a single sapphire wafer was developed to analyze the transient heat conduction in conjunction with the heat radiation and heat convection on the wafer surfaces. A silicon wafer was also investigated, for comparison. It was found that the rapid thermal loading leads to a parabolic radial temperature distribution, which induces thermal stresses even if the wafer is not mechanically restrained. The study predicted that for sapphire wafers the maximum furnace temperature of 800 /spl deg/C should be held for two hours in order to get a uniform temperature throughout the wafer.     

The effect of surface roughness on the radiative properties ofpatterned silicon wafers

The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are not well characterized. We report measurements of room temperature reflectance of a memory die, logic die, and various multilayered wafer backsides. The surface roughness of the die areas and wafer backsides is characterized using atomic force microscopy (AFM). These data are subsequently used to assess the effectiveness of thin film optics in providing approximations for the radiative properties of patterned wafers for RTP applications     

Thermal uniformity of 12-in silicon wafer in linearlyramped-temperature transient rapid thermal processing

This paper presents a systematic method for estimating the dynamic incident-heat-flux profiles required to achieve thermal uniformity in 12-in silicon wafers during linearly ramped-temperature transient rapid thermal processing using the inverse heat-transfer method. A two-dimensional thermal model and temperature-dependent silicon wafer thermal properties are adopted in this study. The results show that thermal nonuniformities on the wafer surfaces occur during ramped increases in direct proportion to the ramp-up rate. The maximum temperature differences in the present study are 0.835°C, 1.174°C, and 1.516°C, respectively, for linear 100°C/s, 200°C/s, and 300°C/s ramp-up rates. Although a linear ramp-up rate of 300°C/s was used and measurement errors did reach 3.864°C, the surface temperature was maintained within 1.6°C of the center of the wafer surface when the incident-heat-flux profiles were dynamically controlled according to the inverse-method approach. These thermal nonuniformities could be acceptable in rapid thermal processing systems     

A model for rapid thermal processing: achieving uniformity throughlamp control

A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures     

Features of defect formation under the thermal treatment of dislocation-free single-crystal large-diameter silicon wafers with the specified distribution of oxygen-containing gettering centers in the bulk

Possibilities of obtaining a defect-free layer in wafers of dislocation-free single-crystal silicon subjected to rapid thermal annealing (RTA) are analyzed. The application of RTA is based on the possibility of effectively affecting the distribution profile of the density of oxygen precipitates over the wafer thickness by means of controlling the distribution profiles of the vacancies and interstitial atoms. However, the solution of this important task encounters the problem of the appearance of large local stresses in the vicinity of the fastening supports of a large-diameter silicon wafer and its bending in the course of RTA, which are caused by its own weight. Using mathematical modeling of the three-dimensional stress-strain state and defect formation in large-diameter silicon wafers in the course of RTA, various methods of fastening the wafers are considered and the possibilities of lowering the stress-strain state of the silicon wafer are determined. A mathematical model taking into account the diffusion-recombination processes of vacancies and interstitial silicon atoms, as well as the formation of vacancy clusters is proposed to describe the defect formation in the course of RTA. Based on this model, temperature-temporal parameters of RTA, which correspond to the required (depleted near the surface) concentration profile of the vacancies and the density and size of the vacancy clusters over the wafer thickness, are determined (heating time, holding time at the highest temperature, the cooling rate of the wafer). The results of the calculations are verified for test samples using optical microscopy and transmission electron microscopy (OM and TEM).     

The effect of patterns on thermal stress during rapid thermalprocessing of silicon wafers

The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport model coupled with a thin film optics model for predicting the effect of patterns on the wafer radiative properties. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results show that pattern-induced temperature nonuniformity can cause plastic deformation during RTP, and that the problem is exacerbated by single-side heating, increased processing temperature, and increased ramp rate. Pattern effects can be mitigated by stepping the die pattern out to the edge of the wafer or by altering the thin film stack on the wafer periphery to make the radiative properties across the wafer more uniform     

Dose perturbation by wafer charging during ion implantation

It was found that the dose uniformity of bare wafers in simultaneous arsenic ion implantation into thickly oxidized silicon wafers and bare silicon wafers varies according to the loading combination of wafers. The implantation was executed using a batch-process machine with a wafer loading disk in which a slit is cut to measure beam current during ion implantation. When an oxide wafer was loaded next to the slit with a beam irradiating the oxide wafer just after the slit, disk transverse motion was slowed, which subjected the middle band region of every bare wafer to a high dose. When an oxide wafer was loaded next to a bare wafer with the beam irradiating the oxide wafer just after the bare wafer, part of the bare wafer adjacent to the oxide wafer was subjected to a low dose. It was experimentally clarified that the bare wafer dose variation is caused by the beam blow-up due to the charging of the oxide wafer     

Thermal uniformity and stress minimization during rapid thermalprocesses

The practical development and implementation of rapid thermal processes will significantly influence the semiconductor fabrication industry. With the capability to perform heat cycles quickly and with low thermal budgets, rapid thermal processors have the potential to supplant conventional thermal systems in the years to come. Currently, rapid thermal processors are unable to match the thermal process uniformity produced in conventional convective-based systems. Using a thermal model to approximate the heating characteristics of silicon wafers, it is possible to determine the effects of time-varying intensity profiles on a wafer during a rapid thermal process. Interpretation of this model shows idealized intensity profiles can maintain thermal uniformity at steady-state temperatures. During thermal transients a dynamic continuously changing profile is required to maintain thermal uniformity. As a predictive tool, this analysis can be used to determine and evaluate dynamic uniformity producing intensity profiles before thermal transients occur within a process. This approach can reduce the accumulation of error during high temperature steps not only by providing thermal uniformity at steady states, but by reducing the initial nonuniformities produced by transitions. This paper will review the wafer model, show the results of an idealized profile for steady-state and transient temperatures, and explain the dynamic profiles required for continuous uniformity     

In situ fault detection of wafer warpage in microlithography

Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability and linewidth control in various processing steps. We proposed in this paper an in situ fault detection technique for wafer warpage in microlithography. Early detection will minimize cost and processing time. Based on first principle thermal modeling, we are able to detect warpage fault from available temperature measurements. Experimental results demonstrate the feasibility and repeatability of the approach. The proposed approach is applicable to other semiconductor substrates.     

Calculation of emissivity of Si wafers

A computer-software, Emissivity, has been developed to calculate the emissivity (ɛ) of silicon wafers of any surface morphology, for a given temperature and dopant concentration. The software uses a combination of ray- and wave-optics approaches to include the interference and the polarization effects necessary for multilayer surface coatings and multi-reflections within thin wafers. The refractive index and the absorption coefficient are calculated as a function of temperature and dopant concentration using an empirical model for an indirect bandgap semiconductor. The results of this model are compared with conventional emissivity calculations and experimental data.     

Prediction of the thickness for silicon wafers sawn by diamond wire saw

A higher yield and lower processing cost for the production of the silicon wafer can be realized by reducing the sliced thickness. However, a larger fracture probability is accompanied with the thinner silicon wafer, which limits the wafer thickness to be reduced. The contradiction between reducing wafer thickness and keeping a smaller fracture probability is an important problem for the industrial production of the silicon wafer. This paper investigates the influences of silicon wafer size and machining defects on the fracture probability in order to understand the essential relationship between damage information and fracture probability adequately. A theoretical model of the fracture probability for silicon wafer is proposed based on the probabilistic fracture mechanics to determine a proper thickness for wafers with different size. Furthermore, one method of predicting a proper thickness for silicon wafers sawn by diamond wire saw is developed. The thickness of 450-mm silicon wafer obtained by this proposed method is 920 µm, which is comparable with the value 925 µm specified by the International Technology Roadmap for Semiconductor. The comparison of these two values reveals the feasibility and correctness of this proposed method. The proposed model in this paper can be used to evaluate the fracture probability and predict a proper thickness for silicon wafers with different size, which is benefit to optimize the processing technology and decrease the breakage ratio for the wafer production.     

Temperature measurement of metal-coated silicon wafers bydouble-pass infrared transmission

We report the measurement of the temperature of metal-coated silicon wafers by a double-pass infrared transmission technique. Infrared light incident on the backside of the wafer passes through the wafer, and is re-emitted out the backside after reflecting off the metal surface on the front side of the wafer. The temperature is inferred by the change in the re-emitted signal due to absorption in the wafer. The work has been demonstrated on double-polished wafers from 100°C to 550°C using wavelengths from 1.1 to 1.55 μm. A method for overcoming limitations of the present arrangement for wafers with a rough backside is proposed