A highly reliable trench DMOSFET employing self-align technique andhydrogen annealing

A novel process technique for fabricating trench double diffused MOSFETs (DMOSFET) using three mask layers is realized in order to obtain cost-effective production capability, higher cell density and current driving capability, and higher reliability. A unit cell with a cell pitch of 2.3~2.4 μm and a channel density of 100 Mcell/in² are obtained. Specific on-resistance is 0.36 mΩ.cm² is obtained with a blocking voltage of 43 V. The highly reliable trench DMOSFET was obtained by the formation of the corner rounding of the hydrogen annealed trench surface     

A novel simplified process for fabricating a very high densityp-channel trench gate power MOSFET

A novel simplified fabrication method of a very high density p-channel trench gate power MOSFET using four mask layers and nitride/TEOS sidewall spacers is realized. The proposed process showed improved on-resistance characteristics of the device with increasing cell density and the cost-effective production capability due to the lesser number of processing steps. By using this process technique, a remarkably increased high density (100 Mcell/inch²) trench gate power MOSFET with a cell pitch of 2.5 μm could be effectively realized. The fabricated device had a low specific on-resistance of 1.1 mΩ-cm² with a breakdown voltage of -36 V     

Chlorobenzene vapor assistant annealing method for fabricating high quality perovskite films

In this study, chlorobenzene (CB) vapor assistant annealing (VAA) method is employed to make high quality perovskite films and produce high efficiency CH₃NH₃PbI_3-xCl_x perovskite solar cells. The perovskite films made by this method present several advantages such as increased crystallinity, large grain size and reduced crystal boundaries compared with those prepared by thermal annealing (TA) method, which is beneficial to charge dissociation and transport in hybrid photovoltaic device. In addition, it is found that the CB VAA method could improve the surface property of perovskite film, resulting in a preferable coverage of PCBM layer and a better interfacial contact between perovskite film and upper PCBM film. Consequently, the short circuit current density (J_sc) of the devices is significantly increased, yielding a high efficiency of 14.79% and an average efficiency of 13.40%, which is 13% higher than that of thermal annealed ones. This work not only put forward a simple and efficient approach to prepare highly efficient perovskite solar cells but also provide a new idea to improve the morphology and interfacial contact in one integration step.     

A novel technique for RTP annealing of compound semiconductors

We introduce for the first time a novel rapid thermal processing (RTP) unit called Zapper™, which has recently been developed by MHI Inc. and the University of Florida, for high temperature thermal processing of semiconductors. This Zapper™ unit is capable of reaching much highertemperatures (>1500°C) than conventional tungsten–halogen lamp RTP equipment and achievinghigh ramp-up and ramp-down rates. We have conducted implant activation annealing studies ofSi⁺-implanted GaN thin films (with and without an AlN encapsulation layer) using the Zapper™ unit at temperatures up to 1500°C. The electrical property measurements of such annealed samples have led to the conclusion that high annealing temperatures and AlN encapsulation are needed for the optimum activation efficiency of Si⁺ implants in GaN. It has clearly been demonstrated that the Zapper™ unit has tremendous potential for RTP annealing of semiconductor materials, especially for wide band-gap (WBG) compound semiconductors that require very high processing temperatures.     

A novel approach for fabricating light-emitting porous polysilicon films

By etching back the as-oxidized polysilicon using reactive ion, a uniform porous polysilicon structure with significant enhancement of photoluminescence (PL) intensity was formed. We further found that the PL peak is centered at around 680 nm and is independent on the porosities or sizes of Si micropores. These results indicate the light emission in the samples should not be a consequence of the quantum confinement. Instead, the 680-nm peak should be due to the non-bridged oxide hole centers (SiO·) at the oxidized grain boundaries of the polysilicon.     

A reliable blind convergence technique for phase-splittingequalizers

This article proposes a technique for providing reliable blind convergence of the phase-splitting equalizer. It is shown that the phase-splitting equalizer is difficult to train blindly with the conventional blind algorithm. The proposed technique modifies the cost function of the blind algorithm so that the two filters of the phase-splitting equalizer constitute a Hilbert pair. We also investigate the steady-state performance of the proposed blind algorithm for high-speed digital transmission application     

A novel high performance SemiSJ-CSTBT with p-pillar under the bottom of the trench gate

A novel high performance SemiSJ-CSTBT is proposed with the p-pillar under the bottom of the trench gate. The inserted p-pillar with the neighbouring n-drift region forms a lateral P/N junction, which can adjust the electric distribution in the forward-blocking mode to achieve a higher breakdown voltage compared to the conventional CSTBT. Also, the p-pillar can act as a hole collector at turn-off, which significantly enhances the turn-off speed and obtains a lower turn-off switching loss. Although the turn-off switching loss decreases as the depth of the p-pillar increases, there is no need for a very deep p-pillar. The associated voltage overshoot at turn-off increases dramatically with increasing the depth of p-pillar, which may cause destruction of the devices. Plus, this will add difficulty and cost to the manufacturing process of this new structure. Therefore, the proposed SemiSJ-CSTBT offers considerably better robustness compared to the conventional CSTBT and SJ-CSTBT. The simulation results show that the SemiSJ-CSTBT exhibits an increase in breakdown voltage by 160 V (13%) and a reduction of turn-off switching loss by approximately 15%.     

Simple technique for fabricating limited coupler gratings byholographic method using standard thick photoresist

The fabrication of photoresist gratings is considered. A solution to the problem of `transversal standing waves' is given and appears simple and versatile     

A reliable molding technique by using epoxy-based resin for thin-film superconducting quantum interference devices

A reliable package is necessary for superconducting devices fabricated with thin films and wirebonds to maintain stable operation and good performance of the devices. In particular, prevention of wirebond disconnection due to thermal cycles is very important. We have developed a reliable epoxy resin and molding technique, which works as a stable package at extremely low temperature. Using this resin to package low-Tc superconducting quantum interference devices (SQUIDs) with aluminum and niobium wirebonds, so far 94.2% of more than 1500 SQUIDs have shown no disconnection of wirebond after ten thermal cycles at 77 K plus once at 4.2 K. We also confirmed that this resin does not generate any magnetic noise and a SQUID can be detrapped with a magnetic flux through thermal conduction from a resistor packaged together with the SQUID.     

Low-cost trench isolation technique for reverse blocking IGBT using boron nitride doping wafers

A new fabrication process for IGBT devices with reverse blocking capability (RB-IGBT) is presented in this paper. The trench isolation approach which provides the reverse blocking capability has been implemented using solid source as doping technique (Boron doping wafers), resulting in a low-cost process in both starting material and time-consuming aspects. The feasibility of the fabrication technique has been validated with the electrical measurements of the prototype devices.     

A novel reliable and secure communication scheme for cognitive radio networks using concatenated kernel codes

Cognitive radio networks have emerged as a possible solution for the spectrum scarcity problem. Cognitive radio networks involve heterogeneous entities as part of it for facilitating spectrum sharing. Ensuring reliability and security in such scenario is inevitable for the licensed users (primary users) as well as for the unlicensed users (secondary users). To address the challenges of reliable and secure communication for the secondary users, in this paper, a novel reliable and secure communication framework is proposed. A class of group codes called concatenated kernel codes is used to achieve reliability and techniques of fundamental cutset and fundamental circuit to achieve security in terms of authentication of sender. It is shown that the proposed communication framework provides reliability mitigating the continuous interference of primary users and security by defending against the cryptanalytic attacks such as replay attack, related key attack, and man‐in‐the‐middle attacks. The theoretical basis of the proposed framework is validated, and its performance is evaluated through simulations.     

A novel insulated gate technology for ingaas high electron mobility transistors using silicon interlayer based passivation technique

A novel insulated gate technology for InGaAs high electron mobility transistors (HEMT) is described. It utilizes a silicon interface control layer (Si ICL)-based passivation structure. By applying an HF surface treatment, the technology becomes applicable to the air-exposed surfaces of InGaAs and InAlAs. The basic metal-insulator-semiconductor structures were fabricated and characterized in detail by x-ray photoelectron spectroscopy analysis and capacitance-voltage measurements. The interface has been shown to be essentially free from interface states. InGaAs insulated gate HEMTs (IGHEMT) were then success-fully fabricated. The fabricated recessed gate IGHEMTs have good gate control of the drain current with good pinch-off characteristics. A highest effective mobility of 2010 cm²/Vs was obtained. The devices show extremely low gate leakage currents below lnA/mm.     

A fast and reliable routing technique for wireless mesh networks

In wireless mesh networks (WMNs), real time communications (e.g., Voice over IP (VoIP) and interactive video communications) may often be interrupted as packets are frequently lost or delayed excessively. This usually happens due to the unreliability of wireless links or buffer overflows along the routing paths. The mesh connectivity within the WMN enables the capability to enhance reliability and reduce delay for such applications by using multiple paths for routing their packets. The vital components in multi‐path routing for achieving this are the pre‐determined formation of paths and the technique that the paths are deployed for packet traversal. Therefore, we propose a novel multi‐path routing protocol by introducing a new multi‐path organization and a traffic assignment technique. The designed technique dubbed as FLASH (Fast and reLiAble meSH routing protocol) discovers one primary path between a pair of source and destination based on a new proposed metric, and thereafter selects mini‐paths, which connect pairs of intermediate nodes along the primary path. The primary path and mini‐paths are concurrently deployed, as multiple copies of packets are routed through. This technique compensates for possible outage at intermediate wireless nodes or their corresponding wireless links along the primary path. Routing along mini‐paths is performed in such a way that redundant copies do not cause an excessive congestion on the network. The effectiveness of the proposed scheme is evaluated analytically and through extensive simulations under various load conditions. The results demonstrate the superiority of the proposed multi‐path organization in terms of reliability and satisfactory achievements of the protocol in enhancing delay and throughput compared to the existing routing protocols, especially for long distances and in congested conditions. Copyright © 2010 John Wiley & Sons, Ltd.     

A novel synthesis technique for conducting scatterers using TLMtime reversal

This paper presents a novel numerical synthesis technique based on the reversal of the TLM process in time. It allows the designer to generate the geometry of a passive structure from its desired frequency response using alternate forward and backward time domain simulations. The essential steps of the procedure are explained and validated using, as an example, the synthesis of an inductive obstacle in a waveguide. If fully developed, it promises to become an advantageous alternative to the traditional techniques using frequency domain numerical methods     

Activation annealing of Si-implanted GaN up to 1500°C using a novel RTP technique

A novel rapid thermal processing (RTP) unit called Zapper™ has recently been developed by MHI Inc. and the University of Florida for high temperature thermal processing of semiconductors. This Zapper™ unit is capable of reaching much higher temperatures (>1500°C) than conventional tungsten-halogen lamp RTP equipment and achieving high ramp-up and ramp-down rates. Implant activation annealing studies of Si⁺-implanted GaN thin films (with and without an AlN encapsulation layer) have been conducted using the Zapper™ unit at temperatures up to 1500°C. The measurements of electrical properties of such annealed samples have led to the conclusion that high annealing temperatures and AlN encapsulation are needed for the optimum activation efficiency of Si⁺ implants in GaN. It has clearly been demonstrated that the Zapper™ unit has tremendous potential for RTP annealing of semiconductor materials, especially for wide bandgap compound semiconductors that require very high processing temperatures.     

A novel trench termination design for 100-V TMBS diode application

In this letter, a novel trench termination structure that can inhibit the reverse leakage current substantially and reduce the process cost is introduced. For trench type power devices, such as trench MOS barrier Schottky (TMBS) diodes, this new termination structure can be processed simultaneously with the active region without any additional mask. Simulation and experimental results show that TMBS diodes with this new termination structure can achieve a reverse blocking voltage of 100 V with a leakage current density as low as 8.4×10^-4 A/cm²     

PLATOP: a novel planarized trench isolation and field oxideformation using poly-silicon

A novel isolation scheme named planarized trench isolation and field oxide formation using poly-silicon (PLATOP) Is described. PLATOP is applicable to high-performance submicron VLSI since it results in encroachment-free shallow trenches, and planarized field oxide. The process offers poly silicon-filled deep trenches. The process also relies on noncritical lithography and novel etch processes to planarize the deposited poly-silicon from the top of the active areas, and oxidation to consume the poly-silicon in the field regions. Electrical results are presented proving the viability of the isolation scheme     

A rapid annealing technique for efficient perovskite solar cells fabricated in air condition under high humidity

A rapid annealing technique for fabricating perovskite materials via microwave radiation in air condition is presented. A planar-heterojunction perovskite device via microwave radiation within 6 min exhibits an efficiency of 10.29%, compared to 11.08% for a 90 min heating-annealed device in inert atmosphere, which is higher than that (8.04%) of a heating-annealed device in air condition under high humidity (∼60%). We believe that the microwave annealing technique provides a fast and less energy-intensive process for fabricating ideal perovskite active layers for high performance solar cells.     

一种高压火焰燃烧检测的新技术——异步光学取样法

1.在通常的泵浦-探测激光光谱测量中,所用的泵浦与探测锁模激光器的锁模脉冲重复频率是相同的.因此需用一光学延迟装置来控制两束激光脉冲之间的相对延迟时间.同时还要采用某种机械或电光的斩波器,产生一振幅调制信号,以便于同步地交流检测.与之对比,新发展的ASOPS技术所使用的泵浦及探测激光脉冲的重复频率f_泵、f_探是略为不同的.它们之间的拍频为f_拍.于是,泵浦和探测激光脉冲系列之间有一渐变的位相延迟.位相延迟量的变化周期为(f_拍)~(-1),如图1(α)所示.该图给出了在泵浦激光脉冲系列的泵浦下,样品处于激发     

A novel LDMOS structure using P-trench for high performance applications

In this paper, we propose a new structure of silicon on insulator (SOI) lateral diffused metal oxide semiconductor (LDMOS) field effect transistors to improve the device performance. In the proposed structure, a trench is created in the buried oxide under the drift and drain regions and filled with p-type Si. We called the proposed structure as P-trench SOI-LDMOS (PT-LDMOS). Our simulations with two dimensional ATLAS simulator shows the unique features exhibited by the proposed structure in comparison with a conventional SOI-LDMOS (C-LDMOS). In the PT-LDMOS, the electric field is modified by producing a new additional peak at the electric field distribution, reducing the magnitude of electric field peak near the gate edge, removing of electric field crowding near the drift and drain junction at the bottom surface of the silicon layer, and making the surface electric field distribution more smooth. We optimize the doping concentration and the dimensions of the P-trench in the PT-LDMOS structure. Hence, the results illustrate the benefits of high performance PT-LDMOS over conventional one and expand the application of SOI-LDMOSs to high voltage.