Analytical I–V model of SOI and SON MOSFETs: a comparative analysis

A generalised three-interface compact capacitive threshold voltage model for horizontal silicon-on-insulator/silicon-on-nothing (SOI/SON) MOSFET has been developed. The model includes different threshold voltage-modifying short-channel phenomena like fringing field, junction-induced 2D-effects, etc. Based on the threshold voltage model, an analytical current voltage model is formulated from the basic charge control analysis of MOSFET. In order to provide a better explanation to various observations and applicable to short-channel SOI and SON structures, the present current voltage model includes the effect of carrier velocity saturation and channel length modulation. Identical structures for both the devices, SOI and SON, are considered but for SON MOSFET, the buried oxide layer is replaced by air. The performance of the two devices are studied and compared in terms of threshold voltage roll-off, subthreshold slope, drain current and drain conductance. The SON MOSFET technology is found to offer devices with further scalability and enhanced performance in terms of threshold voltage roll-off, sub-threshold slope and greater current derivability, thereby providing scope for further miniaturisation of devices and much better performance improvement.     

Silicon-on-Nothing (SON)-an innovative process for advanced CMOS

A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guaranteed by epitaxial process. The SON process' allows the buried dielectric (which may be an oxide but also an-air gap) to be fabricated locally in dedicated parts of the chip, which may present advantages in terms of cost and facility of system-on-chip integration. The SON stack itself is physically confined to the under-gate-plus-spacer area of a device, thus enabling extremely shallow and highly doped extensions, while leaving the HDD (highly doped drain) junctions comfortably deep. Therefore, SON embodies the ideal device architecture taking the best elements from both bulk and SOI and getting rid of their drawbacks. According to simulation results, SON enable ables excellent Ion/Ioff trade-off, suppressed self-heating, low S/D series resistance, close to ideal subthreshold slope, and high immunity to SCE and DIBL down to ultimate device dimensions of 30 to 50 nm     

Ultrathin body SiGe-on-insulator pMOSFETs with high-mobility SiGe surface channels

A novel concept and a fabrication technique of strained SiGe-on-insulator (SGOI) pMOSFET are proposed and demonstrated. This device has an ultrathin strained SiGe channel layer, which is directly sandwiched by gate oxide and buried oxide layers. The mobility enhancement of 2.3 times higher than the universal mobility of conventional universal Si pMOSFETs was obtained for a pMOSFET with 19-nm-thick Si/sub 0.58/Ge/sub 0.42/ channel layer, which is formed by high-temperature oxidation of a Si/sub 0.9/Ge/sub 0.1/ layer grown on a Si-on-insulator (SOI) substrate. A fully depleted SGOI MOSFET with this simple single-layer body structure is promising for scaled SOI p-MOSFET with high current drive.     

Fabrication of ultrathin SOI by SIMOX water bonding (SWB)

Ultrathin silicon-on-insulator (SOI) layers of separation by implantation of oxygen (SIMOX) wafers have been transferred onto thermally oxidized silicon wafers by wafer bonding technology. Due to the technical availability and the complementary nature of SIMOX and wafer bonding approaches, SIMOX wafer bonding (SWB) solves some of the respective major difficulties faced by both SIMOX and wafer bonding for device quality ultrathin SOI mass production: the preparation of adequate buried oxide (including its interfaces) in SIMOX and the uniformly thinning one of the bonded wafers to less than 0.1 μm in wafer bonding. The effect of positive charges in the oxide on bondability of ultrathin SOI films and possible applications of SWB will also be outlined.     

Field and temperature dependence of TDDB of ultrathin gate oxide

The results of an investigation of time-dependent breakdown (TDDB) of intrinsic ultrathin gate oxide are presented for a wide range of oxide fields 4.6ox<10.4 MV/cm at elevated temperatures. It was found that TDDB of ultrathin oxide follows the E model down to 4.6 MV/cm. The data show that TDDB t₅₀ starts deviating from the 1/E model for fields below 7.2 MV/cm. The data also show that the TDDB activation energy for this type of gate oxide is linearly dependent on oxide field. In addition, we show that the field acceleration parameter γ decreases as temperature increases     

基于SON的MOSFET器件及其工艺方法研究

超薄体SOI器件能够有效抑制短沟道效应,业界认为在纳米器件时代它有可能取代传统体硅器件。但SOI器件的全局化埋氧层特性会使其产生自加热效应,严重时会导致器件开态电流下降、漏电流增加,从而导致器件可靠性降低。具有局部空洞层或介质层的SON器件及其制备方法已成为纳米器件时代的一个研究热点。阐述了SON器件的基本概念,比较了SON器件和传统体硅器件的电学特性。对SON器件的工艺制备方法进行了全面描述,包括早期的SON器件制备方法、基于MSTS的SON制备方法、气体注入SON制备方法,以及完全自对准SON器件制备方法。详细描述了准自对准气体注入SON器件和完全自对准SON器件制备方法的工艺流程。     

Self-align recessed source drain ultrathin body SOI MOSFET

In this letter, a self-aligned recessed source/drain (ReS/D) ultrathin body (UTB) silicon-on-insulator (SOI) MOS technology is proposed and demonstrated. The thick diffusion regions of ReS/D are placed on a recessed trench, which is patterned on the buried oxide and go under the SOI film. The new structure reduces the parasitic S/D resistance without increasing the gate-to-drain Miller capacitance, which is the major advantage over the elevated S/D structure. Fabrication details and experimental results are presented. The scalability of the UTB MOSFETs and the larger design window due to reduced parasitics are demonstrated.     

30-nm recessed S/D SOI MOSFET with an ultrathin body and a low SDE resistance

A novel ultrathin body SOI MOSFET with a recessed source-drain (S/D) structure is proposed to reduce the S/D extension (SDE) resistance and the feasibility on the proposed device is checked. A recessed buried oxide under the SDE regions is completely filled with the heavily doped polysilicon, which can lead to a low SDE resistance. A recessed S/D SOI MOSFET with 30 nm gate length and 5 nm thick undoped channel, was successfully fabricated and showed the good SCE immunities; little punch-through, the drain-induced barrier lowering of 140 mV/V, and the subthreshold slope of 79 mV/dec.     

Time dependent breakdown of ultrathin gate oxide

Time dependent dielectric breakdown (TDDB) of ultrathin gate oxide (<40 Å) was measured for a wide range of oxide fields (3.4<|E_ox|<10.3 MV/cm) at various temperatures (100⩽T⩽342°C). It was found that TDDB of ultrathin oxide follows the E model. It was also found that TDDB t₅₀ starts deviating from the 1/E model for fields below 7.2 MV/cm. Below 4.8 MV/cm, TDDB t₅₀ of intrinsic oxide increased above the value predicted by the E model obtained for fields >4.8 MV/cm. The TDDB activation energy for this type of gate oxide was found to have linear dependence on oxide field. In addition, we found that γ (the field acceleration parameter) decreases with increasing temperature. Furthermore, it was found that testing at high temperatures (up to 342°C) and low electric field values did not introduce new gate oxide failure mechanism. It is also shown that TDDB data obtained at very high temperature (342°C) and low fields can be used to generate TDDB model at lower temperatures and low fields. Our results (an enthalpy of activation of 1.98 eV and dipole moment of 12.3 eÅ) are in complete agreement with previous results by McPherson and Mogul. Additionally, it was found that TDDB is exponentially dependent on the gate voltage     

A study of the effects of tunneling currents and reliability of sub-2 nm gate oxides on scaled n-MOSFETs

This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.     

C-V and C-t analysis of buried oxide layers formed by high-dose oxygen implantation

For silicon-on-insulator devices with very thin active layers, the quality of the buried oxide layer and its interface with the top silicon layer can significantly affect device performance. This study focuses on the characterization of buried oxide layers formed by high-dose oxygen implantation into Si wafers. Capacitance-voltage (C-V) and capac-itance-time (C-t) measurements were performed on the epilayer/buried oxide/substrate capacitors. From high frequency C-V measurements, data on fixed oxide charge, inter-face traps, and donor densities were obtained for both buried oxide interfaces, as well as the thickness of the buried oxide layer. From C-t measurements, minority carrier generation lifetimes were calculated for thin depletion regions on both sides of the buried oxide. The data is correlated to changes in implanted dose, anneal temperature, and anneal time.     

Tunneling leakage current in ultrathin (<4 nm) nitride/oxidestack dielectrics

The leakage current in high-quality ultrathin silicon nitride/oxide (N/O) stack dielectric is calculated based on a model of one-step electron tunneling through both the nitride and the oxide layers. The results show that the tunneling leakage current in the N/O stack is substantially lower than that in the oxide layer of the same equivalent oxide thickness (EOT). The theoretical leakage current in N/O stack has been found to be a strong function of the nitride/oxide EOT ratio: in the direct tunneling regime, the leakage current decreases monotonically as the M/O ratio increases, while in the Fowler-Nordheim regime the lowest leakage current is realized with a N/O EOT ratio of 1:1. Due to the asymmetry of the N/O barrier shape, the leakage current under substrate injection is higher than that under gate injection, although such a difference becomes smaller in the lower voltage regime. Experimental data obtained from high quality ultrathin N/O stack dielectrics agree well with calculated results     

Reliability of ultrathin silicon dioxide under combined substratehot-electron and constant voltage tunneling stress

An experimental investigation of breakdown and defect generation under combined substrate hot-electron and tunneling electrical stress of silicon oxide ranging in thickness from 2.0 nm to 3.5 nm is reported. Using independent control of the gate current for a given substrate and gate bias, the time-to-breakdown of ultrathin silicon dioxide under substrate hot-electron stress is observed to be inversely proportional to the gate current density. The thickness dependence (2.0 nm to 3.5 nm) of substrate hot-electron reliability is reported and shown to be similar to constant voltage tunneling stress. The build-up of defects measured using stress-induced-leakage-current and charge-pumping for both tunneling and substrate hot-electron stress is reported. Based on these and previous results, a model is proposed to explain the time-to-breakdown behavior of ultrathin oxide under simultaneous tunneling and substrate hot-electron stress. The results and model provide a coherent understanding for describing the reliability of ultrathin SiO₂ under combined substrate hot-electron injection and constant voltage tunneling stress     

Electroactive Centers at the Outer Interface of an Ultrathin Oxide Layer and Their Effect on the Electrical Performance of Single-Crystal Silicon/Noncrystalline Oxide/Polysilicon Structures

Single-crystal silicon/noncrystalline ultrathin oxide multilayer structures were investigated. The oxide was formed by (100)Si thermal oxidation. An undoped polysilicon layer with an aluminum contact was used as a gate. The distribution of ionized electroactive centers (defects) in the ultrathin oxide and the energy spectrum of the centers at the oxide interfaces and near the polysilicon surface were considered. It was found that the centers at the outer interface of the oxide affect the electrical performance of the multilayer structures.     

High-current small-parasitic-capacitance MOSFET on a poly-Siinterlayered (PSI:Ψ) SOI wafer

A new type of silicon-on insulator (SOI) structure has been fabricated by using direct bonding technology to bury multilayered films consisting of poly-Si and SiO₂. A device with an ideal epitaxial channel structure was fabricated using a conventional MOS process on this novel multilayered SOI (100-nm SOI/10-nm SiO₂/poly-Si/500-nm SiO₂) wafer. In this device, the highly concentrated p⁺ poly-Si just beneath the nMOS channel region acts as a punchthrough stopper, and the buried thin backgate oxide under the SOI layer acts as an impurity diffusion barrier, keeping the impurity concentration in the SOI film at its original low level. The device fabricated was an ultrathin SOI MOSFET capable of operating at a current 1.5 times that of conventional hundred-nm devices at low voltages     

Electrical characteristics of low temperature polysilicon TFT with a novel TEOS/oxynitride stack gate dielectric

This investigation is the first to demonstrate a novel tetraethylorthosilicate (TEOS)/oxynitride stack gate dielectric for low-temperature poly-Si (LTPS) thin film transistors (TFTs), composed of a plasma-enhanced chemical vapor deposition (PECVD) thick TEOS oxide/ultrathin oxynitride grown by PECVD N/sub 2/O-plasma. The stack oxide shows a very high electrical breakdown field of 8.4 MV/cm, which is approximately 3 MV/cm larger than traditional PECVD TEOS oxide. The field effective mobility of stack oxide LTPS TFTs is over 4 times than that of traditional TEOS oxide LTPS TFTs. These improvements are attributed to the high quality N/sub 2/O-plasma grown ultrathin oxynitride forming strong Si/spl equiv/N bonds, as well as to reduce the trap density in the oxynitride/poly-Si interface.     

Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide

The degradation induced by substrate hot electron (SHE) injection in 0.13-/spl mu/m nMOSFETs with ultrathin (/spl sim/2.0 nm) plasma nitrided gate dielectric was studied. Compared to the conventional thermal oxide, the ultrathin nitrided gate dielectric is found to be more vulnerable to SHE stress, resulting in enhanced threshold voltage (V/sub t/) shift and transconductance (G/sub m/) reduction. The severity of the enhanced degradation increases with increasing nitrogen content in gate dielectric with prolonged nitridation time. While the SHE-induced degradation is found to be strongly related to the injected electron energy for both conventional oxide , and plasma-nitrided oxide, dramatic degradation in threshold voltage shift for nitrided oxide is found to occur at a lower substrate bias magnitude (/spl sim/-1 V), compared to thermal oxide (/spl sim/-1.5 V). This enhanced degradation by negative substrate bias in nMOSFETs with plasma-nitrided gate dielectric is attributed to a higher concentration of paramagnetic electron trap precursors introduced during plasma nitridation.     

Characterization and modeling of edge direct tunneling (EDT)leakage in ultrathin gate oxide MOSFETs

This paper examines the edge direct tunneling (EDT) of electron from n⁺ polysilicon to underlying n-type drain extension in off-state n-channel MOSFETs having ultrathin gate oxide thicknesses (1.4-2.4 nm). It is found that for thinner oxide thicknesses, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT) and gate-to-substrate tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model is for the first time derived for the oxide field E_OX at the gate edge by accounting for electron subband in the quantized accumulation polysilicon surface. This model relates E_OX to the gate-to-drain voltage, oxide thickness, and doping concentration of drain extension. Once fox is known, an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well     

超薄氧化门的等离子体充电损伤机理

探讨了金属氧化物半导体场效应管超薄氧化门在等离子体加工中造成的充电损伤机理,应用碰撞电离模型解释了超薄氧化门对充电损伤比厚氧化门具有更强免疫力的原因.     

Skin‐Like Oxide Thin‐Film Transistors for Transparent Displays

Flexible transparent display is a promising candidate to visually communicate with each other in the future Internet of Things era. The flexible oxide thin‐film transistors (TFTs) have attracted attention as a component for transparent display by its high performance and high transparency. The critical issue of flexible oxide TFTs for practical display applications, however, is the realization on transparent and flexible substrate without any damage and characteristic degradation. Here, the ultrathin, flexible, and transparent oxide TFTs for skin‐like displays are demonstrated on an ultrathin flexible substrate using an inorganic‐based laser liftoff process. In this way, skin‐like ultrathin oxide TFTs are conformally attached onto various fabrics and human skin surface without any structural damage. Ultrathin flexible transparent oxide TFTs show high optical transparency of 83% and mobility of 40 cm² V^?1 s^?1. The skin‐like oxide TFTs show reliable performance under the electrical/optical stress tests and mechanical bending tests due to advanced device materials and systematic mechanical designs. Moreover, skin‐like oxide logic inverter circuits composed of n‐channel metal oxide semiconductor TFTs on ultrathin, transparent polyethylene terephthalate film have been realized.