HACS: A novel cost aware paradigm promising fault tolerance on mesh-based network on chip architecture

As the integration of transistors on today’s embedded systems scales, so does the shrinking size of chips, thus making the on-chip communication a challenging issue on the VLSI designs. However, network on chips have emerged as a promising technology to tackle the on-chip communication constraints. Likewise, the reliability issues have become the salient problem, since regarding to the inaccessible failures of on-chip elements, there must be some levels of embedded fault tolerance techniques. In this paper, an innovated technique is revealed providing fault tolerance in the on-chip networks over single and multiple permanent switch failures. The experimental results achieved by the system simulation in SystemC TLM environment are validated with the mathematical analysis modeled for system reliability that we extend in this paper, which demonstrate the extensive reliability enhancement of this paradigm. Along with the system improvement, silicon area overhead is calculated utilizing VHDL low level simulation and Orion synthesis.     

Testing embedded-core-based system chips

Recently, designers have been embedding reusable modules to build on-chip systems that form rich libraries of predesigned, preverified building blocks. These embedded cores make it easier to import technology to a new system and differentiate the corresponding product by leveraging intellectual property advantages. Most importantly, design reuse shortens the time-to-market for new systems. The attributes that make system chips built with embedded IP cores an attractive methodology-design reuse, heterogeneity, reconfigurability, and customizability-also make testing and debugging these chips a complex challenge. The authors review the various alternatives for testing embedded cores and describe solutions and proposed standards that are expected to play a key role in developing the core based design paradigm     

A scalable and fault-tolerant network routing scheme for many-core and multi-chip systems

Current on-chip network and inter-chip interconnection are designed separately. However, this traditional design methodology faces a great challenge: in a multi-chip system, each many-core chip contains hundreds or thousands of processors. The increasing number of on-chip processors must share one input/output unit to interface with the inter-chip interconnection. The increased network usage at the chip interface may create an uneven traffic load in the on-chip network. That is, traffic jams could occur in the chip area around the input/output unit. New technologies, such as through silicon via and silicon interposer, can directly connect networks on chips. These technologies can improve communication performance and reduce power consumption by omitting the input/output unit. This paper proposes a novel routing scheme to deal with the network scalability issues related to the many-core and multi-chip system-in-package paradigm. The proposed scheme can also enhance the fault-tolerance of nano-scale communication in deep-submicron designs.     

Chip-level integration of RF MEMS on-chip inductors using UV-LIGA technique

This paper presents a chip-level integration of radio-frequency (RF) microelectromechanical systems (MEMS) air-suspended circular spiral on-chip inductors onto MOSIS RF circuit chips of LNA and VCO using a multi-layer UV-LIGA technique including SU-8 UV lithography and copper electroplating. A high frequency simulation package, HFSS, was used to determine the layout of MEMS on-chip inductors with inductance values close to the target inductance values required for the RF circuit chips within the range of 10%. All MEMS on-chip inductors were successfully fabricated using a contrast enhancement method for 50 μm air suspension without any physical deformations. High frequency measurement and modeling of the integrated inductors revealed relatively high quality factors over 10 and self-resonant frequencies more than 15 GHz for a 1.44 nH source inductor and a 3.14 nH drain inductor on low resistivity silicon substrates (0.014 Ω cm). The post-IC integration of RF MEMS on-chip inductors onto RF circuit chips at a chip scale using a multi-layer UV-LIGA technique along with high frequency measurement and modeling demonstrated in this work will open up new avenues with the wider integration feasibility of MEMS on-chip inductors in RF applications for cost-effective prototype applications in small laboratories and businesses.     

LOCST: A Built-In Self-Test Technique

A built-in self-test technique utilizing on-chip pseudorandom-pattern generation, on-chip signature analysis, a ``boundary scan' feature, and an on-chip monitor test controller has been implemented on three VLSI chips by the IBM Federal Systems Division. This method (designated LSSD on-chip self-test, or LOCST) uses existing level-sensitive scan design strings to serially scan random test patterns to the chip's combinational logic and to collect test results. On-chip pseudorandom-pattern generation and signature analysis compression are provided via existing latches, which are configured into linear-feedback shift registers during the self-test operation. The LOCST technique is controlled through the on-chip monitor, IBM FSD's standard VLSI test interface/controller. Boundary scan latches are provided on all primary inputs and primary outputs to maximize self-test effectiveness and to facilitate chip I/O testing. Stuck-fault simulation using statistical fault analysis was used to evaluate test coverage effectiveness. Total test coverage values of 81.5, 85.3, and 88.6 percent were achieved for the three chips with less than 5000 random-pattern sequences. Outstanding test coverage (≫97%) was achieved for the interior logic of the chips. The advantages of this technique, namely very low hardware overhead cost (≪2%), design-independent implementation, and effective static testing, make LOCST an attractive and powerful technique.     

Multi-hop communications on wireless network-on-chip using optimized phased-array antennas

Network-on-Chip (NoC) as a promising design approach for on-chip interconnect fabrics could overcome the energy as well as synchronization challenges of the conventional interconnects in the gigascale System-on-Chips (SoC). The advantages of communication performance of traditional wired NoC will no longer be continued by the future technology scaling. Packets that travel between distant nodes of a large scale wired on-chip network significantly suffer from energy dissipation and latency due to the routing overhead at each hop. According to the International Technology Roadmap for Semiconductors annual report, the RFCMOS characteristics will be steadily improved by technology scaling. As the operating frequency of RF devices increases, the size of Si integrated antenna will decrease and it is feasible to employ them as a revolutionary interconnect for intra-chip wireless communications. In this paper, we focus on physical requirements and design challenges of wireless NoC. It is demonstrated that employing an optimum-radiation phased array antenna and multihop communications will increase the reliability of on-chip wireless links by several orders of magnitude using a limited power budget less than 0.1 pJ/bit.     

人工智能范式的革命与通用智能理论的创生

人工智能的研究取得了不少可喜的进展,也面临着许多严峻的挑战.为了应对这些挑战,学术界提出了各种各样的研究思路.笔者相信,每种思路都有其合理之处,都有可能获得一定的成效.不过,根据笔者的理解,人工智能面临的最深刻最严峻的挑战,是学科和时代的大转变所带来的大阵痛:人工智能范式的张冠李戴.因此,必须对人工智能的范式实施"正冠...     

片上多处理器末级Cache优化技术研究

片上多核技术的出现给处理器的设计和实现带来很多挑战,片上存储系统的设计就是其中最重要的方面之一.为了缓解日益严峻的存储墙问题,研究者们通常在片上放置大容量末级Cache,片上末级Cache设计和优化技术已成为当前的研究热点.介绍了片上多处理器(CMP)末级Cache设计面临的挑战,然后分别介绍了以私有设计和共享设计为基础的多种CMP末级Cache优化技术,并对它们进行了比较分析.     

Cyber-physical model for efficient and secured operation of CPES or energy Internet

If your computer crashes, you can revive it by a reboot, an empirical solution that usually turns out to be effective. The rationale behind this solution is that transient faults, either in hardware or software, can be fixed by refreshing the machine state. Such a “silver bullet”, however, could be futile in the future because the faults, especially those existing in the hardware such as Integrated Circuit (IC) chips, cannot be eliminated by refreshing. What we need is a more sophisticated mechanism to steer the system back to the right track. The “magic cure” is the Fault Tolerance On-Chip (FTOC) mechanism, which relies on a suite of built-in design-for-reliability logic, including fault detection, fault diagnosis, and error recovery, working in a self-supportive manner. We have exploited the FTOC to build a holistic solution ranging from on-chip fault detection to error recovery mechanisms to address faults caused by chips progressively aging. Besides fault detection, the FTOC paradigm provides attractive benefits, such as facilitating graceful performance degradation, mitigating the impact of verification blind spots, and improving the chip yield.

     

Embedded software-based self-test for programmable core-baseddesigns

The programmable cores on SoCs can perform on-chip test generation, measurement, response analysis, and even diagnosis. This software-based approach to self-testing enables at-speed testing and incurs low DFT overhead. We give an overview of the existing embedded software-based self-testing and self-diagnosis methods for core-based SoC designs, and we discuss the challenges to further developing this new testing paradigm     

深亚微米SoC芯片的可测试性设计

深亚微米工艺使SoC芯片集成越来越复杂的功能,测试开发的难度也不断提高。由各种电路结构以及设计风格组成的异构系统使测试复杂度大大提高,增加了测试时间以及测试成本。描述了一款通讯基带SoC芯片的DFT实现,这款混合信号基带芯片包含模拟和数字子系统,IP核以及片上嵌入式存储器,为了满足测试需求,通过片上测试控制单元,控制SoC各种测试模式,支持传统的扫描测试以及专门针对深亚微米工艺的,操作在不同时钟频率和时钟域的基于扫描的延迟测试模式,可配置的片上存储器的BIST操作以及其它一些特定测试模式。     

Toward on-chip datacenters: a perspective on general trends and on-chip particulars

Due to economical reasons, the traditional philosophy in data centers was to scale out, rather than scaling up. However, the advances in CMP technology enabled chip multiprocessors to become more prevalent and they are expected to become more affordable and power-efficient in the coming years. Current trend towards more densely packaged systems and increasing demand for higher performance push the market towards placing datacenters on highly powerful chips that have many cores on a single platform. However, increasing the number of cores on a single chip brings along very important problems to be addressed at the chip level regarding the use of shared resources and QoS satisfaction. After briefly exploring current datacenter perspective, this paper captures the current state of the art in the field of chip multiprocessors through a detailed discussion of different studies that pave the way to the datacenters on-chip. Finally, a number of open research issues are highlighted with the intention of inspiring new contributions and developments in the field of datacenters on-chip.     

A digital signal processor with IEEE floating-point arithmetic

A overview is given of Motorola's DSP96002, a digital signal processor that implements IEEE-standard floating-point arithmetic. It is designed for graphics, image processing, spectral analysis and scientific computing applications. Performance peaks at 40.5 Mflops (million floating-point operations per second) and 13.5 MIPS (million instructions per second) and 18 Mflops on assembly-language benchmarks. The DSP is software-compatible with the fixed-point 56000/1 family architecture and instruction set. The 96002 achieves compatibility with other processors and databases, higher mathematical accuracy, and better error handling than implementations that do not conform to the IEEE standard. The 96002's on-chip memories, dual-bus architecture, and transparent DMA are suitable for multiprocessor systems in which many 96002s connect with minimum external components. These features result in a smaller-footprint, lower-cost system than other microprocessors or data-path chips. On-chip support for the fast access modes of external memories achieves near-SRAM (static random-access memory) performance with high-density DRAM/VRAM (dynamic RAM/virtual RAM) devices. An on-chip circuit emulation controller provides full access and control of the machine state for system debugging. A variety of software and hardware development tools support the 96002     

Will physical scalability sabotage performance gains?

The most important physical trend facing chip architects is the fact that on-chip wires are becoming much slower relative to logic as the on-chip devices shrink. The author points out that it will soon be impossible to maintain one global clock over the entire chip, and sending signals across a billion-transistor processor may require as many as 20 cycles     

Guest Editors' Introduction: On-Chip Interconnects for Multicores

This special issue of IEEE Micro brings readers the latest advances in the field of on-chip interconnects for multicores. The guest editors specifically selected articles to focus on novel on-chip networks realized on actual silicon--partly to showcase a few silicon prototypes of on-chip networks being used in multicore processors and SoCs; partly to bring to attention the implementation issues facing architects and designers. Along with six articles that gather insights from the designers of actual on-chip interconnects for multicores, the special issue includes two articles that delve into the design infrastructure support for on-chip networks and an article that summarizes the grand research challenges for realizing next-generation on-chip networks and multicores.     

基于片上网络的多核芯片组通讯方案

多芯片协同工作是一种廉价、低风险的高密度计算应用解决方案。由于片上网络(Network On Chip,NoC)的数据通讯具有并发、分离的特性,因此可以方便地在板级集成多块NoC多核芯片协同工作,构成NoC多核芯片组,快速提供更强大的处理能力。基于某高性能图像处理项目,其硬件系统主要由4块NoC多核芯片构成,4块芯片采用全互连方式,研究了报文数据在不同多核芯片间的传输问题,提出了一种通过硬件实现的多核芯片组通讯方案,该方案已应用在某高性能图像处理项目。     

Inhibition of on-chip PCR using PDMS–glass hybrid microfluidic chips

In the course of developing a microfluidic analytical platform incorporating the polymerase chain reaction (PCR) and subsequent capillary electrophoresis (CE) analysis for a variety of bio-assays, we examined PCR inhibition through surface interactions with the chip materials. Our devices perform PCR in a three-layer chip, a glass–poly(dimethylsiloxane)–glass sandwich in which the poly(dimethylsiloxane) (PDMS, a silicone rubber) layer is used for pneumatic membrane pumping and valving of the PCR reagents. Initial on-chip PCR–CE tests of BK virus replicated in multiple uncoated chips showed variable results, usually yielding no detectable product at the target sample concentrations used. Subsequent “chip-flush” experiments, where water or reagents were flushed through a chip and subsequently incorporated in off-chip PCR, highlighted bovine serum albumin (BSA) amongst other pre-treatments, chip materials and PCR recipes as being effective in mitigating inhibition. When the BSA channel pre-coating was applied to on-chip PCR–CE experiments, a substantial improvement (10× to 40×) in signal-to-noise (S/N) of the CE product peak was conferred, and was shown with high confidence despite high S/N variability. This is the first study to quantitatively examine BSA’s ability to reduce inhibition of PCR performed on PDMS chips, and one of very few microfluidic PCR inhibition studies of any kind to use a large number of microfluidic chips (~400). The simplicity and effectiveness of our BSA coating suggest that passivating materials applied to microfluidic device channel networks may provide a viable pathway for development of bio-compatible devices with reduced complexity and cost.     

Guest Editors' Introduction: The Evolution of RFIC Design and Test

There are several challenges facing RFIC design and test. The demand in the wireless market will drive RFIC products. For RFIC chipsets, improvements are needed for the elimination of passive components, better integrated passives, power reduction, modeling of devices and interconnects, packaging, and cost-effective testing. However, this innovation cannot come at the cost of time to market for new products. Also, development costs must be driven to a minimum, as average selling prices for RFICs remain flat or decline. Moreover, one of the biggest challenges in moving from low GHz to higher frequencies is the lack of integration between the production testing infrastructure, EDA tools, and device designs. Advancements in device and test equipment modeling and simulation technology are beginning to bridge this gap. Finally, RF measurement requires specialized capital equipment investments and highly skilled engineers with many years of experience. This special issue on design and test of RFIC chips describes some of these challenges and proposes some interesting solutions.