Gate oxide breakdown on nMOSFET cutoff frequency and breakdown resistance

Gate oxide breakdown effect on CMOS RF devices has been examined. The breakdown spot resistance and total gate capacitance of nMOS transistors decrease with stress. The analytical equation of cutoff frequency including the gate oxide breakdown effect is derived. The impact of oxide breakdown on the performance of an LC oscillator is evaluated. The oscillation frequency of the LC oscillator increases with oxide breakdown.     

A study of parallel tuner with voltage‐dependent capacitance

A study of varactor tuned LC circuits is presented. Nonlinear time domain circuit differential equation is rewritten in terms of phase plane variables, which can then be solved in closed form. General expressions are derived, which are applicable to any capacitance–voltage relationship. Two types of circuit structures, namely single‐ended and balanced, with MOS diodes as the variable capacitance elements, are specifically considered. The nature of the voltage waveforms across the two circuits is determined by phase plane plots. Variation of voltage with time is calculated numerically. It is shown that the voltage waveform for the single‐ended circuit is asymmetric, with higher harmonics present. Furthermore, the fundamental resonant frequency is dependent on amplitude of oscillation and could decrease to 94% of its small signal value for large voltage swings. Near 34% control over frequency is calculated, for a bias voltage range of 8 to 1. On the other hand, the balanced structure results in symmetric voltage waveform, with negligible harmonic content. Dependence of frequency on amplitude is weak, only decreasing to 98% of its small signal value, for the largest swings. The tuning range is marginally improved by the balanced structure. The results are compared with those obtained from Fourier‐based calculations and experimental data in literature, and good agreement is obtained. Copyright © 2011 John Wiley & Sons, Ltd.     

Transformer‐coupled π‐network differential CMOS oscillator circuit topology

This paper reports a novel oscillator circuit topology based on a transformer‐coupled π‐network. As a case study, the proposed oscillator topology has been designed and studied for 60 GHz applications in the frame of the emerging fifth generation wireless communications. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. The root‐locus analysis shows that oscillations occur only at that resonant frequency of the LC tank. Moreover, a closed‐form expression for the quality factor (Q) of the LC tank is derived which shows the enhancement of the equivalent quality factor of the LC tank due to the transformer‐coupling. Last, a phase noise analysis is reported and the analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations in the Cadence design environment with a 28 nm CMOS process design kit commercially available. Copyright © 2016 John Wiley & Sons, Ltd.     

Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

This study developed a local oscillator (LO) with low phase noise and low power consumption. The proposed oscillator core comprises a pair of cross‐coupled transistors, which are fed by another pair of transistors that injects current at moments close to the peak of output voltage. The position of the current injection transistors, which are inserted in series with the cross‐coupled transistors, affects the waveform of current injected into an inductive–capacitive (LC) tank. Installing a capacitor on the source node of the cross‐coupled transistors increases the current injected into the LC tank and thereby augments the output voltage amplitude and power efficiency of the LO. The resonator phase shift and Q can be corrected by adjusting the source capacitance, which filters noise. These changes reduce the phase noise to ?123.4 dBc/Hz at a frequency offset of 1 MHz and improve oscillator performance with a figure of merit equal to ?193.5 dBc/Hz. To evaluate the LC tank, a 5 GHz LO was simulated at 1.8 V power supply and 2.5 mW power consumption. The simulation was conducted using a practical 0.18 complementary metal–oxide–semiconductor model manufactured by the Taiwan Semiconductor Manufacturing Company. The simulation results confirmed the analytical findings.     

Frequency–amplitude relations for cross‐coupled voltage‐controlled oscillator

Dependence of frequency on amplitude and control bias is considered for the cross‐coupled voltage‐controlled oscillator. Closed form expressions are derived for frequency of oscillation as a function of amplitude, for positive and negative control bias voltages. Theory of nonlinear ordinary differential equations is utilized to show that the capacitance–voltage relation is the main cause of frequency shift with amplitude. Furthermore, the case of small amplitudes relative to control voltage is analyzed, and a closed form expression is derived for dependence of frequency on amplitude. This relation is then verified using the concept of effective capacitance. The effective capacitance approach is also used to extend the analysis to large voltage swings. Dependence of frequency on tuner control voltage is calculated for both bias polarities. Implications of the aforementioned equations for voltage‐controlled oscillator performance are discussed. Numerical calculations and simulations are used to compare and verify the closed form equations, showing good agreement. Copyright © 2012 John Wiley & Sons, Ltd.     

Stability analysis of wideband linear bipolar varactor‐controlled oscillator with two‐coupled resonant circuits

Theoretical analysis of the stability conditions of the steady‐state operation modes and tuning bandwidth characteristics of bipolar self‐biased varactor‐controlled oscillator (VCO) with two‐coupled resonant circuits are presented. The recommendations at the choice of the circuit and varactor parameters for a linearization of the wideband tuning frequency characteristics under free‐running stable oscillation conditions are given. Highly linear octave‐band tuning operation was found to be possible using hyper‐abrupt varactors in two‐coupled resonant circuits VCO. Numerical and experimental results verify the validity of the design approach described. Copyright © 1999 John Wiley & Sons, Ltd.     

Short‐term stability in the intermediate region between quartz crystal oscillation and LC oscillation

In a quartz crystal oscillator circuit, an LC resonance circuit was inserted that enabled major enlargement of the variable range of frequency compared with the conventional Colpitts or Pierce quartz crystal oscillator. The short‐term stability of the oscillation was measured with Allan variance in the intermediate region between the quartz resonance and LC resonance, showing higher stability compared with the common LC oscillator. The analytical result is presented showing continuous transition from the quartz resonance to the LC resonance. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A 3.6‐mW 6‐GHz current‐reuse VCO‐buffer with improved load drivability in 65‐nm CMOS

A new current‐reuse voltage‐controlled oscillator (VCO)‐buffer with enhanced load drivability is proposed. It incorporates a PMOS‐based source follower stacked atop a NMOS‐based LC VCO to share the bias current, while preventing the voltage stress at any oscillation node from exceeding the 1.2‐V technology voltage limit. Also, ac‐coupling networks are avoided between the VCO and buffer, improving the Q of the LC tank while minimizing parasitics. With internal buffering, the VCO can directly drive up a 50‐Ω load for testing, or to withstand a large capacitive load in on‐chip local oscillator distribution, particularly suitable for multi‐band MIMO WLAN radios . The fabricated VCO‐buffer in 65‐nm CMOS measures 13.8% tuning range from 5.64 to 6.4 GHz, consumes 3.6 mW at 1.2 V and exhibits ?108.84 dBc/Hz phase noise at 1‐MHz offset. Copyright © 2013 John Wiley & Sons, Ltd.     

A series‐coupled LC quadrature oscillator using phase/amplitude calibration

In this paper, an analytic approach for the estimation of the phase and amplitude error in series coupled LC quadrature oscillator (SC‐QO) is proposed. The analysis results show that imbalances in source voltage of coupling transistor because of mismatches between LC tanks are the main source of the phase and amplitude error in this oscillator. For compensation of the phase and amplitude error, a phase and amplitude‐tunable series coupled quadrature oscillator is designed in this paper. A phase shift generation circuit, designed using an added coupling transistor, can control the coupling transistor source voltage. The phase and amplitude error can simply be controlled and removed by tuning the phase shifter, while this correction does not have undesirable impact on phase noise. In fact, the proposed SC‐QO generates a phase shift in the output current, which reduces the resonator phase shift (RPS) and improves phase noise. The phase and amplitude tunable SC‐QO is able to correct the phase error up to ±12°, while amplitude imbalances are reduced as well. To evaluate the proposed analysis, a 4.5‐GHz CMOS SC‐QO is simulated using the practical 0.18‐μm TSMC CMOS technology with a current consumption of 2 mA at 1.8‐V supply voltage. Copyright © 2016 John Wiley & Sons, Ltd.     

Analysis of power-frequency trade-offs in millimeter-wave CMOS oscillators

In this paper, considering the nonlinear effects in two ports consisting of transistor, a general method is proposed for estimating the amplitude of high-frequency ring oscillators. The proposed method can be generalized to various structures that can be disassembled into similar two ports. Moreover, in each CMOS process, a design procedure can be followed to obtain the desired output power and frequency. This is the first time that the frequency and amplitude of oscillator are related to each other in a system of nonlinear equations. First, considering the maximum achievable oscillation frequency, the analysis of ring oscillator structure is performed for the given output power. The results show that the proposed structure operates at 7 to 18% higher oscillation frequency compared with conventional structures. In the next step, assuming that the oscillator structure and passive network topology are known, another system of nonlinear equations is defined for designing the oscillator for the given frequency and amplitude of oscillation. Finally, the implicit solution, which includes the passive network elements connecting to the transistor, is obtained. The results of equations follow the simulation results with an acceptable error (1% frequency error and about 5% amplitude error).     

A wide variable‐range CMOS–VCXO for IC

Recently, miniaturization, low power consumption, and high‐frequency stability have been required in crystal oscillators as a frequency source, because of the rapid development of mobile communications, typified by cellular phones. Usually, a VCXO (Voltage Controlled Crystal Oscillator) has been included in PLL. And it has been required that the VCXO should be implemented on a CMOS–IC chip. The oscillating frequency of a traditional VCXO has been controlled by capacitance variation of a varactor diode. But it is difficult to implement the varactor diode on an IC chip. In our previous study, we showed that a transistor VCXO utilizing the MOSFET's Miller capacitance of a variable capacitance circuit had a wide frequency variable range. On the other hand, in a CMOS–VCXO, the Miller capacitance has decreased. Therefore, a wide frequency variable range could not be obtained by utilizing the Miller capacitance in the CMOS–VCXO. In this paper, first, a variable capacitance circuit is realized in order to construct a wide‐variable‐range CMOS–VCXO for IC. The variable capacitance circuit is composed of a MOSFET as a voltage controlled resistance. Next, the CMOS–VCXO is constructed by the variable capacitance circuit and a CMOS crystal oscillator. As a result, we show that the CMOS–VCXO has a wide frequency variable range of about 400 ppm.© 1999 Scripta Technica, Electr Eng Jpn, 130(3): 49–56, 2000     

A numerical model for the oscillation frequency,the amplitude and the phase‐noise of MOS‐current‐mode‐logic ring oscillators

This paper presents a new model for the frequency of oscillation, the oscillation amplitude and the phase‐noise of ring oscillators consisting of MOS‐current‐mode‐logic delay cells. The numerical model has been validated through circuit simulations of oscillators designed with a typical 130 nm CMOS technology. A design flow based on the proposed model and on circuit simulations is presented and applied to cells with active loads. The choice of the cell parameters that minimize phase‐noise and power consumption is addressed. Copyright © 2009 John Wiley & Sons, Ltd.     

石英晶体振荡器负载电容的匹配设计

介绍了石英晶体振荡器的结构和主要参数、负载电容的匹配设计和电路负阻的测量计算,以及晶体驱动功率的测量计算。针对实际应用中因谐振阻抗不匹配而出现的振荡电路不起振、频率偏差较大等现象,优化设计了基于舰用断路器电量监测模块实际应用的晶体振荡电路。     

A new CMOS astable multivibrator and its nonlinear analysis

We present a nonlinear analysis of a new inductively tuned astable multivibrator obtained by connecting a timing inductor across a composite nonlinear resistor with a characteristic of N‐type, which is made up of the parallel connection of two complementary pairs of cross‐coupled MOS devices. Some possible practical applications of the circuit are also envisaged. Closed‐form expressions for the amplitude and the period of the periodic oscillation are derived in both cases when the circuit exhibits a relaxation oscillation and in the more difficult case when, due to the effect of parasitic capacitances of the devices, the circuit has an almost‐discontinuous relaxation oscillation with a nonzero switching time. The accuracy of the presented formulas, which are useful for both the analysis and design, is validated through circuit simulations and experimental results. Copyright © 2009 John Wiley & Sons, Ltd.     

Phase error analysis in CMOS injection‐coupled LC quadrature oscillator (IC‐QO)

This paper presents a novel approach to study the phase error in source injection coupled quadrature oscillators (QOs). Like other LC QOs, the mismatches between LC tanks are the main source of phase error in this oscillator. The QO is analyzed where the phase error and oscillation frequency are derived in terms of circuit parameters. The proposed analysis shows that the output phase error is a function of injection current and the current of source equivalent capacitor. As a result, it is shown that increasing of tail current and LC tank quality factor decreases the phase error. Derived equations show that the phase error can be cancelled and even controlled by adjusting bias currents. To evaluate the proposed analysis and consequent designed QO, a 5.5 GHz CMOS QO is designed and simulated using the practical 0.18 µm TSMC CMOS technology. The experiments show good agreement between analytical equations and simulation results. Copyright © 2013 John Wiley & Sons, Ltd.     

Phase noise analysis in CMOS differential Armstrong oscillator topology

This paper reports a phase noise analysis in a differential Armstrong oscillator circuit topology in CMOS technology. The analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations for oscillation frequencies of 1, 10, and 100 GHz. The analysis captures well the phase noise of the oscillator topology and shows the impact of flicker noise contribution as the major effect leading to phase noise degradation in nano‐scale CMOS LC oscillators. Copyright © 2016 John Wiley & Sons, Ltd.     

Suppression of overtone oscillation and low‐current operation using novel‐design scheme for quartz crystal oscillators

A novel design is proposed for a low‐frequency quartz crystal oscillator circuit. Negative resistance in a low‐frequency CMOS‐inverter quartz oscillator was reviewed for the fundamental mode at 32 kHz and the overtone oscillation at 200 kHz. Suppression of the overtone oscillation, appropriate gain, and drive current reduction are realized by adding only three circuit components. Experimental results and an estimate of the absolute value of the negative resistance are presented for the conventional Colpitts circuit and two types of the quartz crystal oscillator circuit. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

高性能MOS结构高频C-V特性测试仪

MOS结构高频C-V(电容-电压)特性测量是检测MOS器件制作工艺的重要手段。本阐述了用高频检测法测量MOS电容的原理,介绍了用变频技术和集成芯片设计MOS结构高频C-V特性测试仪的方法。该测试仪电路简单,成本低,分辨率高,测量准确,稳定性好。     

Charge-based capacitance measurements (CBCM) on MOS devices

A new simple method of measuring capacitance-voltage characteristics of MOS devices is presented. Proceeding from the charge-based capacitance measurement technique suggested recently, a compact test structure with high resolution has been developed, which only requires measurement of do quantities. The method was tested on a 0.6-μm CMOS process with small and large area capacitors and compared to well-known high-frequency capacitance-voltage results. Beside using a reference structure, a second means of extracting parasitic effects is demonstrated for small structures. The test structure allows measurements in a wide frequency range with high accuracy and low noise contribution at small capacitance levels     

主绝缘劣化对变频电机宽频开关振荡特性的影响

为研究主绝缘劣化对变频电机开关瞬态宽频振荡特性的影响,建立了计及功率器件开关暂态过程和主绝缘状态的变频调速系统宽频域模型,分析了宽频开关振荡电流的主导模态及其传导路径,探索主绝缘电容变化对开关振荡电流幅频响应特征的作用规律。仿真和实验结果表明：开关振荡电流主要包含高频差模、高频共模和中频共模3个主导模态分量。开关振荡中频共模分量电流可以渗透进电机绕组内部,其幅频响应特征与主绝缘电容参量有关：共模串联谐振频率随主绝缘电容增加而减小,靠近串联谐振点的幅值特征随主绝缘电容增加而增加,从而为变频电机绝缘在线状态监测提供了一种新的思路。