基于ARM7内核和嵌入式系统的VME总线控制器的研制

简要介绍了一种VME式总线控制器的设计方法。三星公司的S3C4510B是一款采用了ARM7内核的支持网络连接的高性能16／32位RISC处理器,采用它和相关芯片研制出了类似3U的VME总线控制器,嵌入式操作系统为uClinux。该控制器主要给设备总线提供高速网络连接通道,把后台计算机数据库和前端总线设备紧密地连接起来,实现数据的快速获取与给定。     

基于FPGA的VME总线控制器及其驱动程序

本文论述了用于兰州重离子加速器冷却储存环(HIRFL-CSR)前端控制系统的总线控制器的FPGA设计及其基于ARM-Linux下的驱动程序设计.该总线控制器采用Altera公司的ACEX系列中的EP1K30实现,通过VME总线背板同其它VME设备(CPLD)通信,可读VME设备数据,监视电源运行状况,也可向VME设备发送命令和写数据,并且能够响应VME设备中断,读中断数据.为了能够通过AT91RM9200控制器访问VME总线控制器,必须为其编写相应的驱动程序.驱动程序定义了应用程序调用接口和数据格式,并实现了中断机制、多进程访问和数据的突发(burst)读写.     

嵌入式Web服务器在VME总线测试系统中的应用

介绍了嵌入式Web服务器Wind Web Server的原理和关键技术,并利用嵌入式Web服务器技术实现了一套VME总线测试软件,该软件可用于VME协议所支持的基本功能测试.     

BESⅢ触发系统径迹计数插件的设计与实现

本文介绍BESⅢ触发系统径迹计数插件的设计与实现.该插件实现128通道的径迹计数功能,并输出触发条件;插件支持VME总线的读写操作和CBLT在线数据读出;所有功能在FPGA中实现,并以流水线工作方式工作.具备通过VME总线在线加载FPGA的功能.经过测试,插件达到了预期的设计目标,并已应用到BESⅢ工程MDC宇宙线实验中.     

EPICS在VxWorks操作系统下访问VME设备的应用研究

EPICS是由美国阿贡国家实验室(ANL)和洛斯阿拉莫斯国家实验室(LANL)联合开发的控制系统软件包.PCI是一种局部总线,用于连接计算机中的硬件设备.VME是一种异步总线,稳定可靠,在EPICS控制系统中应用广泛.开发EPICS的VME总线驱动程序,需要对计算机的地址映射等机制有充分的了解,因此需要对这些内容进行研...     

基于多处理机的并行实时计算机

在当今计算机应用领域里,能进行并行计算的实时计算机系统越来越引起人们的关注。 本文所述的是一种采用多个处理机构成的并行实时计算机开发系统。该系统使用运行UNIX操作系统的VAX-11/750或MC68000 CPU的个人计算机为宿主计算机,具有ETHERNET网路支持。采用VME总线支持系统,使处理机插件可以互相联接,也可以通过“VME总线一网络”接口与宿主计算机联接。宿主计算机将生成的程序目标代     

并行设备总线电源控制系统设计

为实现CSRe试验环磁铁电源的控制同步,采用32位ARM内核芯片技术结合DSP控制板方式,稳定可靠地实现控制数据流的传输和同步事例的收发。同时通过CPLD逻辑时序编程来设计eVME正背板总线系统。本系统用嵌入式网络和并行总线技术可靠稳定实现数据的快速获取与给定。     

基于StreamDevice的VME机箱监测及其应用研究

VME总线具高可靠性与稳定性的优点,使得其在加速器控制中得到了广泛应用。Stream Device是EPICS的一个通用设备支持模块,用来与支持字节流的设备进行通信。由于加速器运行的需要,很有必要对VME机箱的当前运行状态进行实时监测。Schroff公司提供的CMM模块,可用于监测VME机箱或CPCI机箱的状态。以VME机箱为例,阐述了如何使用CMM模块对机箱状态进行监测及利用Stream Device把状态变量接入到EPICS系统中的方法,并简单介绍了在CSNS定时系统中的应用。     

VME总线在线"从串模式"配置FPGA的设计与实现

本文介绍了在线配置FPGA硬件设计及工作原理.所设计的系统可以使FPGA的配置数据通过VME总线写入到一片Flash Memory中,并在加电时或使用命令的方式通过Flash Memory来配置FPGA.另外,FPGA的配置数据还可以直接保存在PC机终端上,而不是Flash Memory中,在需要时,通过VME总线直接将配置数据配置给FPGA.     

一个基于VxWorks和PowerPC的VME插件测试系统

介绍了一个基于VxWorks和PowerPC的VME插件测试系统TTL的设计及其功能.该测试系统允许硬件开发人员在不同的层次上对VME插件进行常见功能的调试和检测,包括VME总线读写操作、CBLT(Chained Block Transfer),MCST(Multicast)以及IACK(中断响应)测试.在BES Ⅲ的电子学系统VME机箱和插件级设备的调试和检测中采用了该测试系统,提高了硬件研制及调试的效率.     

A high speed, fibre optic, link for Digital Equipment CorporationVAXes

The authors describe an optical fiber link that is used in conjunction with the CERN host interface family to connect high-performance VAXes to VMEbus or FASTBUS over distances up to 1000 m. The modular construction allows other permutations, including VAX/VAX, FASTBUS/FASTBUS, VMEbus/VMEbus, or FASTBUS/VMEbus connections, over similar distances. The link comprises two identical optical data interconnects (ODI) connected by two unidirectional multimode fibers. The ODI at each end of the link can be connected to any device conforming to the DRB32 user interface specification. The authors discuss the operation of an ODI, the testing of the optical link, and present and future ODI implementations     

A VMEbus interface for multi—detector trigger and control system

MUSE（MUltiplicity SElector)is the trigger and control system of CHIMERA,a 4π charged particles detector.Initialization of MUSE can be performed via VMEbus.This paper describes the design of VMEbus interface and functional module in muse,and briefs an application of MUSE.     

Fast VMEbus interface for NIM ADC's

A high performance VMEbus interface module for NIM ADC's has been developed. Data pipelining and data suppression speed up the data acquisition. An event synchronization module for coincidence experiments has also been designed     

一个VME总线接口电路

简要介绍了一个VME总线接口电路，该接口电路是为一个中能核反应实验系统多参数数据获取系统的TRIGGER设计研制的。该接口电路可支持32位单周期传输和链式块数据传输（即CBLT传输方式）。     

基于DSP的智能模数变换插件设计

介绍了一个基于ＤＳＰ，用于采集北京谱仪实验数据的智能模数变换插件的设计方法。此插件是为替代ＳＬＡＣ于８０年代生产的类产品而设计的。插件上的ＤＳＰ实现了实时数据预处理功能。同时使用了ＦＰＧＡ构造ＶＭＥ总线接口，提高了集成度。     

嵌入式Linux系统在PowerPC上的实现

介绍了一个在PowerPC上建立嵌入式Linux操作系统的应用实例.该系统的主要目的是用于VME总线设备的测试,也可用于小型数据获取与控制系统.建立系统的过程中充分考虑到软件开发以及PowerPC的特点,为开发者提供两种可选的程序编译测试方法.介绍了几种典型嵌入式操作系统,比较商业嵌入式系统与主流Linux嵌入式系统的异同以及它们的优缺点;就如何根据特定目标板建立一个可裁减的嵌入式Linux操作系统做了详细的阐述;给出了一个可以成功运行的测试实例.     

加速器中的三维磁铁CAD系统及其初步应用

文章叙述了一个三维磁铁CAD系统MCAD,其前处理软件能灵活地对各种三维场域进行自动剖分,形成三棱柱单元;基于双标量位法的磁场分析软件,同时采用了直接迭代和NEWTON-RAPHSON迭代,较好地解决了非线性情况下收敛速度慢的问题;后处理软件除了能显示磁场强度外,还可计算和显示带电粒子在空间的运动轨迹、各典型场区的相图、加速过程中粒子的滑相情况以及其它物理参数,使得MCAD能更好地满足加速器领域三维磁铁CAD的要求。最后绘出MCAD的检验和应用实例,说明MCAD具有目前国际上通用有限元法计算三维静磁场的计算精度,能适应实际设计的需要。     

ECH system developments including the design of an intelligent fault processor on the DIII-D tokamak

A new generation fault processor is in development which is intended to increase fault handling flexibility and reduce the number of incomplete DIII-D shots due to gyrotron faults. The processor, which is based upon a field programmable gate array device, will analyze signals for aberrant operation and ramp down high voltage to try to avoid hard faults. The processor will then attempt to ramp back up to an attainable operating point. The new generation fault processor will be developed during an expansion of the electron cyclotron heating (ECH) areas that will include the installation of a depressed collector gyrotron and associated equipment. Existing systems will also be upgraded. Testing of real-time control of the ECH launcher poloidal drives by the DIII-D plasma control system will be completed. The ECH control system software will be upgraded for increased scalability and to increase operator productivity. Resources permitting, all systems will receive an extra layer of interlocks for the filament and magnet power supplies, added shielding for the tank electronics, programmable filament boost shape for long pulses, and electronics upgrades for the installation of the advanced fault processor.     

A Dedicated Line-Processor as Used at the SHF

A hardwired trigger processor was used at the SLAC Hybrid Facility to find evidence for charged tracks originating from the fiducial volume of a 40? rapid-cycling bubble chamber. Straight-line projections of these tracks in the plane perpendicular to the applied magnetic field were searched for using data from three sets of proportional wire chambers (PWC). This information was made directly available to the processor by means of a special digitizing card. The results memory of the processor simulated read-only memory in a 168/E processor and was accessible by it. The 168/E controlled the issuing of a trigger command to the bubble chamber flash tubes. The same design of digitizer card used by the line processor was incorporated into the 168/E, again as read only memory, which allowed it access to the raw data for continual monitoring of trigger integrity. The design logic of the trigger processor was verified by running real PWC data through a FORTRAN simulation of the hardware. This enabled the debugging to become highly automated since a step by step, computer controlled comparison of processor registers to simulation predictions could be made.