Automatic VT extractors based on ann×n2 MOS transistor array and theirapplication

The development of incremental and decremental V_T extractors based on the square-law characteristic and an n ×n² transistor array is described. Different implementations have been discussed and the effect of nonidealities such as mobility reduction, channel-length modulation, mismatch, and body effect has been analyzed. Besides automatic V_T extraction, parameter K of an MOS transistor can also be extracted automatically using the V_T extractor, without any need of calculation and delay, and the extracted V_T and K are, respectively, in voltage and current. Experimental results are presented and indicate that the differences between extracted values using the V_T extractor and the most popular numerical method are as small as 0.15% and 0.064%. Additional applications, such as in level shifting, temperature compensation, and temperature measurement, where the V_T extractor can be used either as a PTAT sensor or as a centigrade sensor, are presented     

Oxide charge buildup and spread-out during channel-hot-carrierinjection in NMOSFETs

Oxide charge buildup during channel-hot-carrier (CHC) injection was investigated by the use of a modified charge-pumping technique. An apparent `turnaround' effect in local oxide charge density during low gate voltage (V_T<V_g<1/2 V_d) stressing was observed. It can be explained by the dynamic evolution of the damage location caused by the continuous changes in the electric field distribution during CHC. Dependence on channel length is also presented     

Application of the floating-gate technique to the study of then-MOSFET gate current evolution due to hot-carrier aging

The evolution of the gate current-voltage (I_g- V_gs) characteristics of n-MOSFETs induced by DC stresses at different gate voltage over drain voltage (V_ds ) ratios is studied by the floating-gate (FG) measurement technique. It is shown that the I_g-V_gs curves are always lowered after aging, and that the kinetics are dependent on the aging conditions. A time power law is representative of the V_gs=V_ds case. It is demonstrated that electron traps are created in the oxide by both hot-hole and hot-electron injection stresses. They are not present in the devices before aging. They can be easily charged and discharged by short electron and hole injections, respectively     

The effect of channel hot-carrier stressing on gate-oxide integrityin MOSFETs

The correlation between channel hot-carrier stressing and gate-oxide integrity is studied. It is found that channel hot carriers have no detectable effect on gate-oxide integrity even when other parameters (e.g., ΔV_T and ΔI _D) have become intolerably degraded. In the extreme cases of stressing at V_G≈V_T with measurable hole injection current, however, the oxide charge to breakdown decreases linearly with the amount of hole fluence injected during the channel hot-hole stressing. This may limit the endurance of a nonvolatile memory using hot holes for erasing. This can also explain the gate-to-drain breakdown of a device biased in the snap-back region, since snap-back at low gate voltage is favorable for hole injection. Snap-back-induced oxide breakdown could be an ESD (electrostatic discharge) failure mechanism     

High-frequency InP/InGaAs double heterojunction bipolar transistorson Si substrate

Self-aligned high-frequency InP/InGaAs double heterojunction bipolar transistors (DHBTs) have been fabricated on a Si substrate. A current gain of 40 was obtained for a DHBT with an emitter dimension of 1.6 μm×19 μm. The S parameters were measured for various bias points. In the case of I_C=15 mA, f _T was 59 GHz at V_CE=1.8 V, and f _max was 69 GHz at V_CE=2.3 V. Due to the InP collector, breakdown voltage was so high that a V_CE of 3.8 V was applied for I_C=7.5 mA in the S-parameter measurements to give an f_T of 39 GHz and an f_max of 52 GHz     

Importance of source and drain resistance to the maximum fT of millimeter-wave MODFETs

The usual approximate expression for measured f_T =[g_m/2π (C_gs+C _gd)] is inadequate. At low drain voltages just beyond the knee of the DC I-V curves, where intrinsic f _t is a maximum for millimeter-wave MODFETs, the high values of C_gd and G_ds combine with the high g_m to make terms involving the source and drain resistance significant. It is shown that these resistances can degrade the measured f_T of a 0.30-μm GaAs-AlGaAs MODFET from an intrinsic maximum f_T value of 73 GHz to a measured maximum value of 59 GHz. The correct extraction of maximum f_T is essential for determining electron velocity and optimizing low-noise performance     

A high-performance 0.5-μm BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5-μm BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 μm² by creating self-aligned bit-sense and V_ss contacts. A WSi_x polycide emitter n-p-n transistor with an emitter area of 0.8×2.4 μm² provides a peak cutoff frequency (f_T) of 14 GHz with a collector-emitter breakdown voltage (BV_CFO) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f_T and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process     

Short-channel pMOSTs in a high-resistivity silicon substrate. II.Noise performance

For pt.I, see ibid., vol.39, no.10, p.2268-77 (1992). The noise performance, important for the use of p-channel transistors on high-resistivity silicon in analog applications, is investigated. This is done for the two operation modes: bulk (|V_gs|<|V_T|) and surface (| V_gs|>|V_T|). For the studied transistors, both modes are characterized by a 1/f noise spectrum extending to frequencies of up to ≈100 Hz, and followed by a white-noise spectrum, determined by the substrate resistance     

A pseudomorphic AlGaAs/n+-InGaAs metal-insulator-dopedchannel FET for broad-band, large-signal applications

Molecular beam epitaxy (MBE)-grown L_g=1.7-μm pseudomorphic Al_0.38Ga_0.62As/n⁺-In_0.15Ga _0.85As metal-insulator-doped channel FETs (MIDFETs) are presented that display extremely broad plateaus in both f_T and f_max versus V_GS, with f_T sustaining 90% of its peak over a gate swing of 2.6 V. Drain current is highly linear with V_GS over this swing, reaching 514 mA/mm. No frequency dispersion in g _m up to 3 GHz was found, indicating the absence of electrically active traps in the undoped AlGaAs pseudoinsulator layer. These properties combine to make the pseudomorphic MIDFET highly suited to linear, large-signal, broadband applications     

A high-speed, small-area, threshold-voltage-mismatch compensationsense amplifier for gigabit-scale DRAM arrays

A high-speed small-area DRAM sense amplifier with a threshold-voltage (V_T) mismatch compensation function is proposed. This sense amplifier features a novel hierarchical data-line architecture with a direct sensing scheme that uses only NMOS transistors in the array, and simple V_T mismatch compensation circuitry using a pair of NMOS switching transistors. The layout area of the sense amplifier is reduced to 70% of that of a conventional CMOS common I/O sense amplifier due to the removal of PMOS transistors from the array. The readout time is improved to 35% of that of a conventional CMOS sense amplifier because of direct sensing and a 1/10 reduction in V_T mismatch. This sense amplifier eliminates the sensitivity degradation and the area overhead increase that are expected in gigabit-scale DRAM arrays     

Improved hot-carrier immunity in submicrometer MOSFETs withreoxidized nitrided oxides prepared by rapid thermal processing

The fabrication of 0.8-μm MOSFETs using 7.7-nm-thick nitrided oxides reoxidized by rapid thermal processing at 900-1150°C for 15-200 s is described. The hot-carrier-induced degradation was studied in terms of subthreshold swing, threshold voltage V_T, and transconductance g_m voltage characteristics. Results indicate that rapid reoxidation markedly improves hot-carrier immunity; lifetimes reaching 30-mV V _T shift and 10 percent g_m degradation are improved by 3 and 1.5 orders of magnitude compared with those for thermal oxides, respectively. A degradation characteristic inherent to the (reoxidized) nitrided-oxide system is found, based on the gate-voltage dependence of g_m degradation     

The new two-dimensional electron gas base HBT (2DEG-HBT):two-dimensional numerical simulation

The bipolar/FET characteristics of the 2DEG-HBT are analyzed extensively by a two-dimensional numerical simulator based on a drift-diffusion model. For bipolar operations at high collector current densities, it is confirmed that the cutoff frequency f_T is determined mainly by the collector transit time of holes and by the charging time of the extrinsic base-collector capacitance C _bc^EXT. The charging times of the emitter and base regions and the base transit time are shown to be negligible. A high cutoff frequency F_T (88 GHz) and current gain h_FE (760) are obtained for an emitter size of 1×10 μm², and undoped collector thickness of 150 nm, and a collector current density J_c of 10⁵ A/cm². The FET operation of the same 2DEG-HBT structure shows a threshold voltage V_th of 0.74 V, the transconductance G_m^max of 80 mS/mm, and maximum cutoff frequency F_T^max of 15 GHz. The dependence of the device performance on material parameters is analyzed extensively from a device design point of view     

A coupled study by floating-gate and charge-pumping techniques ofhot carrier-induced defects in submicrometer LDD n-MOSFET's

The creation of defects by hot-carrier effect in submicrometer (0.85-μm) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from V_d/8 to V_d) by hot-hole and/or hot-electron injections, and their generation rates (10^-9 and 10^-2 for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the I_d-V_g degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I _d-V_g degradation     

The effect of surface recombination on the frequency-dependentcharacteristics of an ion-implanted GaAs OPFET

The effect of modulation frequency and surface recombination on the characteristics of an ion-implanted GaAs OPFET is determined analytically. The drain-source current is found to decrease with the increase in both modulation frequency and trap center density. The current changes significantly with the trap center density only when the latter is greater than 10²⁰/m². The threshold voltage does not change appreciably with the modulation frequency as in a silicon OPFET. However, the increased in the trap center density causes V_T to increase in the enhancement device and decrease in the depletion device. Further, V_T increases under the normally ON condition and decreases under the normally OFF condition with an increase in the photon absorption coefficient in GaAs. Some anomalous behavior is observed for higher values of the absorption coefficient     

Optimized trench MOSFET technologies for power devices

Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V_DB =55 V (R_sp=0.2 mΩ-cm², k _D=5.7 Ω-pF) and V_DB=35 V (R_sp=0.15 mΩ-cm², k_D =4.3 Ω-PF) were developed where V_DB is the drain-source avalanche breakdown voltage, R_sp is the specific on-state resistance, and k_D=R _spC_sp is the input device technology factor where C_sp is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model     

A novel and effective PECVD SiO2/SiN antireflectioncoating for Si solar cells

It is shown that sequential plasma-enhanced chemical vapor deposition (PECVD) of SiN and SiO₂ can produce a very effective double-layer antireflection (AR) coating. This AR coating is compared with the frequently used and highly efficient MgF₂/ZnS double layer coating. The SiO₂/SiN coating improves the short-circuit current (J_SC) by 47%, open-circuit voltage (V_OC) by 3.7%, and efficiency (Eff) by 55% for silicon cells with oxide surface passivation. The counterpart MgF₂/ZnS coating gives similar but slightly smaller improvement in V_OC and Eff. However, if silicon cells do not have the oxide passivation, the PECVD SiO₂/SiN gives much greater improvement in the cell parameters, 57% in J_SC, 8% in V_OC, and 66% in efficiency, compared to the MgF₂/ZnS coating which improves J_SC by 50%, V_OC by 2%, and cell efficiency by 54%. This significant additional improvement results from the PECVD deposition-induced surface/defect passivation. The internal quantum efficiency (IQE) measurements showed that the PECVD SiO₂/SiN coating a absorbs fair amount of photons in the short-wavelength range (<500 nm); however, the improved surface/defect passivation more than compensates for the loss in J_SC and gives higher improvement in the cell efficiency compared to the MgF₂/ZnS coating     

A new technique for measuring MOSFET inversion layer mobility

An experimental technique for accurately determining both the inversion charge and the channel mobility μ of a MOSFET is presented. With this new technique, the inversion charge is measured as a function of the gate and drain voltages. This improvement allows the channel mobility to be extracted independent of drain voltage V_DS over a wide range of voltages (V_DS=20-100 mV). The resulting μ(V_GS) curves for different V_DS show no drastic mobility roll-off at V _GS near V_TH. This suggests that the roll-off seen in the mobility data extracted using the split C- V method is probably due to inaccurate inversion charge measurements instead of Coulombic scattering     

A multiple-state memory cell based on the resonant tunneling diode

The device consists primarily of several molecular-beam-epitaxy (MBE-) grown GaAs/(AlGa)As resonant tunneling diodes connected in parallel. This device exhibits multiple peaks in the I-V characteristic. When a load resistor is connected, the circuit can be operated in a multiple stable mode. With this concept, implementation of three-state and four-state memory cells are made. In the three-state case the operating points at voltages V₀=0.27 V , V₁=0.42 V, and V₂=0.53 V represent the logic levels 0, 1, and 2. Similarly for the four-state memory cell the logic levels voltages are V₀=0.35 V, V₁=0.42 V, V₂=0.54 V, and V ₃=0.59 V. A suggestion of an integrated device structure using this concept is also presented     

Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

The effect of silicon gate microstructure and gate oxide process onthreshold voltage instabilities in p+-gate p-channel MOSFETswith fluorine incorporation

Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V_TP) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V_TP shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO₂/Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V_TP shift