PCM混合主存系统的写感知主存管理算法

相变存储器(phase change memory,PCM)凭借字节可寻址,读取速度快(纳秒级),高存储密度,低能耗等优点,在目前基于DRAM(dynamic random access memory)的主存扩展达到瓶颈的情形下,已经成为最具前途的主存存储介质之一,但是PCM有高写延迟,寿命有限等缺陷,因此出现了DRAM/PCM混合主存架构。提出了一种以减少PCM写和保持命中率为目标的混合主存管理算法——写感知的CLOCK算法(CLOCK with a write-aware strategy,CLOCKW)。已有研究主要基于写临近信息(recency of writes,RW)来预测页面写热度,CLOCKW引入内在写距离(inter-write-distance,IWD)概念,并结合写临近信息来预测页面写热度,从而把写密集页面放置在DRAM。此外,CLOCKW通过记录有限的历史写操作信息,将新置换进的页面放在合适的存储介质,避免不必要的页面迁移。最后,基于CLOCK算法的CLOCKW满足虚拟主存管理的低代价要求。实验显示,CLOCKW在保持命中率前提下,可以有效减少PCM写次数。     

基于BKDRHash的混合内存损耗均衡算法研究

相变存储器(PCM)是一种新型的非易失性存储器(NVM),与传统内存DRAM互有优势。基于DRAM和PCM的混合内存使得同时发挥DRAM与PCM各自的优势成为可能。然而,由于PCM写操作寿命有限,在设计混合内存的管理策略时,不仅要对混合内存体系结构进行设计,还需要设计一种损耗均衡算法对PCM写操作进行负载均衡优化。文中设计了一种损耗均衡算法,将写操作逻辑地址作为输入,使用BKDRHash函数对地址进行映射,实现PCM的损耗均衡。实验结果表明,文中提出的损耗均衡算法能够以很少的时延与功耗损失大幅提升PCM的使用寿命。     

基于SRAM和PRAM混合主存设计

由于DRAM芯片超高的静态功耗,使得利用DRAM构建高性能计算机系统中的大容量主存遇到能耗过大问题,这激发了对新型大容量主存结构的研究。针对上述问题,设计了一种基于SRAM和PRAM的混合主存系统,该系统将SRAM作为PRAM的专用写缓存,并将改进后的LRFU算法应用到SRAM写缓存,从而在对主存系统性能影响不大的前提下,有效降低主存系统的能耗和延长PRAM的可用时间。仿真结果显示,所设计的混合存储结构的能耗-延时积（EDP）为纯DRAM存储结构的40%;此外,与纯PRAM存储结构相比,可使PRAM的写操作次数下降28.5%,与将SRAM作为Cache相比,PRAM写次数下降13%。     

基于相变存储器的存储系统与技术综述

随着处理器和存储器之间性能差距的不断增大,"存储墙"问题日益突出,但传统DRAM器件的集成度已接近极限,能耗问题也已成为瓶颈,如何设计扎实有效的存储架构解决存储墙问题已成为必须面对的挑战.近年来,以相变存储器(phase change memory,PCM)为代表的新型存储器件因其高集成度、低功耗的特点而受到了国内外研究者的广泛关注.特别地,相变存储器因其非易失性及字节寻址的特性而同时具备主存和外存的特点,在其影响下,主存和外存之间的界限正在变得模糊,将对未来的存储体系结构带来重大变化.重点讨论了基于PCM构建主存的结构,分析了其构建主存中的写优化技术、磨损均衡技术、硬件纠错技术、坏块重用技术、软件优化等关键问题,然后讨论了PCM在外存储系统的应用研究以及其对外存储体系结构和系统设计带来的影响.最后给出了PCM在存储系统中的应用研究展望.     

一种高效的混合内存布局机制与编码技术

随着大数据和多核技术的发展,传统内存技术的发展已经远远不能满足大量数据密集型应用涌现所催生的内存计算需求。近年来,新型非易失性存储器(NVM)的兴起与发展为打破传统内存技术瓶颈提供了契机。相变存储器(PCM)作为一种典型的新型非易失性存储器(NVM),与传统内存DRAM各有优势,被认为是最有可能代替传统内存DRAM的存储器,在内存应用中具有很好的发展前景。基于DRAM和PCM的混合内存使得同时发挥DRAM与PCM各自的优势成为可能,故提出一种DRAM与PCM混合内存架构,设计针对混合内存布局的高效读写策略及数据迁移机制,并且在混合内存系统中应用纠删码来提高系统的可靠性。实验表明,此混合内存系统能够大大减少能耗,提高数据吞吐量,同时保证读写的可靠性。     

基于相变存储器的存储技术研究综述

以数据为中心的大数据技术给计算机存储系统带来了机遇和挑战.传统的基于动态随机存储器(DRAM)器件的内存面临工艺尺寸缩小至2X nm及以下所带来的系统稳定性、数据可靠性等问题;相变存储器(PCM)具有非易失性、存储密度高、功耗低、抗辐射干扰等优点,且读写性能接近DRAM,是未来最有可能取代DRAM的非易失存储器,它为存储系统的研究和设计提供了新的解决方案.文中在归纳相变存储器器件发展和研究现状的基础上,对相变存储器在系统级的应用方式和面临的问题进行了比较和分析,研究了基于相变存储器的内存技术和外存技术,分析了当前在PCM的寿命、写性能、延迟、功耗等方面所提出的解决方案,指出了现有方案的优势和面临的缺陷,并探讨了未来的研究方向,为该领域在今后的发展提供了一定的参考.     

基于PCM的大数据存储与管理研究综述

大数据已经成为当前学术界和工业界的一个研究热点.但由于计算机系统架构的限制,大数据存储与管理在性能、能耗等方面均面临着巨大的挑战.近年来,一种新型存储介质——相变存储器(phase Change Memory,PCM)——凭着其非易失、字节可寻址、读取速度快、低能耗等诸多优点,为计算机存储体系结构和数据管理设计带来了新的技术变革前景,也为大数据存储和管理带来了新的契机.PCM既是一种非易失存储介质,同时又具备了内存的字节可寻址和高速随机访问特性,模糊了主存和外存的界限,有望突破原有的存储体系架构,实现更高性能的存储与数据管理.概述了PCM存储器的发展现状;总结了目前基于PCM的持久存储技术和基于PCM的主存系统等方面的研究进展;并讨论了PCM在多个领域的应用现状.最后,给出了基于PCM的大数据存储与管理研究的若干未来发展方向,从而为构建新型存储架构下的大数据存储与管理技术提供有价值的参考.     

基于布隆过滤器的新型混合内存架构磨损均衡策略

相变存储器（PCM）凭借低功耗的优势有望成为新一代主存储器,但是耐受性的缺陷成为其广泛应用的重要障碍。现有的随机存取存储器（DRAM）缓存技术和磨损均衡分别从减少PCM写数量以及均匀化写操作分布两个角度延长PCM使用寿命,但前者在写回数据时未考虑数据的读写倾向性,后者在空间局部性较强的应用场景下存在数据交换粒度、空间开销、随机性等诸多问题。因此,设计一种全新的混合存储架构,结合最近最少使用（LRU）算法和带有时间变化的最不经常使用（LFU-Aging）算法提出区分数据读写倾向性的缓存策略,并且基于布隆过滤器（BF）设计针对强空间局部性工作集的动态磨损均衡算法,在有效减少冗余写操作的同时实现低空间开销的组间磨损均衡操作。实验结果表明,该策略能够减少PCM上13.4%~38.6%的写操作,同时有效均匀90%以上分组的写操作分布。     

利用SIMD向量化的数据流软错误检测算法

由于现代处理器不断缩减芯片上元件尺寸、速度不断提高，会导致严重的可靠性问题.针对现有基于冗余的数据流软检错算法效率低下问题，本文提出一种基于SIMD向量化的数据流软错误检测算法VBSED,利用单指令多数据流并行性来提高软件冗余算法的效率，将原代码与冗余代码转换为高效率的SIMD代码，生成具有检错能力的加固程序.对比实验结果表明本文提出的算法可降低加固代码的时空开销，该算法还具有现有算法一般不能检测缓存等部件软错误的优点，并通过故障注入实验验证本文算法在寄存器、缓存和主存部件具有更高的错误检错率.     

飞行模拟器自动着陆系统的建模与仿真

对飞行模拟器自动着陆系统进行了研究.现有的研究多集中在进近阶段,而对接地、拉平以及复飞阶段的研究不够,或并没有统一在相同的控制结构中,使得自动着陆系统的功能和性能无法满足高等级飞行模拟器的指标要求.为了完善自动着陆控制过程,提出了一个完整的自动着陆系统控制律算法,基于典型飞行控制系统体系结构,分别建立了制导回路和姿态回路的控制模型,并进行仿真.算法结果能够满足自动着陆过程中所有飞行阶段对控制算法的功能要求和性能要求,仿真结果表明了控制算法的有效性.     

Robust performance in hybrid-memory cooperative caches

Modern servers require large main memories, which so far have been enabled by increasing DRAM’s density. With DRAM’s scalability nearing its limit, Phase-Change Memory (PCM) is being considered as an alternative technology. PCM is denser, more scalable, and consumes lower idle power than DRAM, while exhibiting byte-addressability and access times in the nanosecond range. Still, PCM is slower than DRAM and has limited endurance. These characteristics prompted the study of hybrid memory systems, combining a small amount of DRAM and a large amount of PCM. In this paper, we leverage hybrid memories to improve the performance of cooperative memory caches in server clusters. Our approach entails a novel policy that exploits popularity information in placing objects across servers and memory technologies. Our results show that (1) DRAM-only and PCM-only memory systems do not perform well in all cases; and (2) when managed properly, hybrid memories always exhibit the best or close-to-best performance, with significant gains in many cases, without increasing energy consumption.     

A space allocation and reuse strategy for PCM-based embedded systems

Phase change memory (PCM) has emerged as a promising candidate to replace DRAM in embedded systems, due to its appealing properties, such as zero leakage power, scalability, shock-resistivity and high density. However, it can only sustain a limited number of write operations. On the other hand, as a program in embedded systems usually distributes write traffic in an extremely unbalanced way, which could further decrease PCM lifetime.In this paper, we propose a space-based wear leveling technique in software compiler level by exploiting the program-specific features. The basic idea is to extend frequently written variables into specific-sized arrays, and evenly distribute writes on allocated array. In such way, we can effectively distribute the write traffic of the program across the whole PCM chip. A space allocation and reuse (SAR) strategy and a polynomial-time algorithm are proposed to produce optimal and near-optimal space allocation, respectively, for achieving a balanced write distribution. The experimental results show our technique can greatly extend the lifetime of PCM-based embedded systems compared with the previous work, and achieve approximately 94% the theoretical maximum of lifetime. Compared with a baseline scheme without wear-leveling mechanism, our technique introduces no more than 0.8% extra writes and 0.7% running overhead.     

A hybrid memory architecture supporting fine-grained data migration

Hybrid memory systems composed of dynamic random access memory (DRAM) and Non-volatile memory (NVM) often exploit page migration technologies to fully take the advantages of different memory media. Most previous proposals usually migrate data at a granularity of 4 KB pages, and thus waste memory bandwidth and DRAM resource. In this paper, we propose Mocha, a non-hierarchical architecture that organizes DRAM and NVM in a flat address space physically, but manages them in a cache/memory hierarchy. Since the commercial NVM device–Intel Optane DC Persistent Memory Modules (DCPMM) actually access the physical media at a granularity of 256 bytes (an Optane block), we manage the DRAM cache at the 256-byte size to adapt to this feature of Optane. This design not only enables fine-grained data migration and management for the DRAM cache, but also avoids write amplification for Intel Optane DCPMM. We also create an Indirect Address Cache (IAC) in Hybrid Memory Controller (HMC) and propose a reverse address mapping table in the DRAM to speed up address translation and cache replacement. Moreover, we exploit a utility-based caching mechanism to filter cold blocks in the NVM, and further improve the efficiency of the DRAM cache. We implement Mocha in an architectural simulator. Experimental results show that Mocha can improve application performance by 8.2% on average (up to 24.6%), reduce 6.9% energy consumption and 25.9% data migration traffic on average, compared with a typical hybrid memory architecture–HSCC.     

基于DRAM牺牲Cache的异构内存页迁移机制

当海量数据请求访问异构内存系统时,异构内存页在动态随机存储器(dynamic random access memory,DRAM)和非易失性存储器(non-volatile memory,NVM)之间进行频繁的往返迁移.然而,应用于传统内存页的迁移策略难以适应内存页"冷""热"度的快速动态变化,这使得从DRAM迁移至N...     

面向DRAM和NVM异构混合内存架构的排序连接算法优化

随着计算机技术的高速发展,数据的应用规模也在不断扩大,各行各业对于数据存取速度的要求也越来越高.为了满足这种需求,内存数据库的思想被提出,然而传统的内存存储器DRAM由于密度和能耗的限制无法大规模集成和扩展.与此同时,非易失内存(NVM)以其性能高、密度高、能耗低的优势弥补了DRAM的不足.DRAM和NVM结合在一起组...     

Memory organizations for 3D-DRAMs and PCMs in processor memory hierarchy

In this paper, we describe and evaluate three possible architectures for using 3D-DRAMs and PCMs in the processor memory hierarchy. We explore: (i) using 3D-DRAM as main memory with PCM as backing store; (ii) using 3D-DRAM as the Last Level Cache and PCM as the main memory; and (iii) using both 3D-DRAM and PCM as main memory. In each of these configurations, since the proposed memories are significantly faster than today’s off-chip 2D DRAMs for main memories and magnetic hard drives for secondary storage, we introduce hardware assistance to speedup virtual to physical address translation.We use Simics, a full system simulator, and benchmarks from both SPEC and OLTP suites to evaluate our designs. We use CACTI for obtaining energy and latency values for our configurations. We measure energy consumed and execution performance for the selected benchmarks.Our studies lead to the following conclusions. The best performance is obtained when 3D-DRAMs are used as last level caches (LLC) and PCM as the main memory. However, this organization performs poorly in terms of energy consumed. Our 3D-DRAM together with PCM as main memory is the best choice in terms of energy consumed. In terms of write-backs, 3D-DRAM as LLC causes fewer writes to PCM than the other organization.These experiments can be extended to explore specific memory organizations, capacities of 3D-DRAM needed as LLC or main memory and how the hybrid PCM/DRAM memory should be used for specific application contexts.     

Exploiting write power asymmetry to improve phase change memory system performance

Phase change memory (PCM) is a promising candidate to replace DRAM as main memory, thanks to its better scalability and lower static power than DRAM. However, PCM also presents a few drawbacks, such as long write latency and high write power. Moreover, the write commands parallelism of PCM is restricted by instantaneous power constraints, which degrades write bandwidth and overall performance. The write power of PCM is asymmetric: writing a zero consumes more power than writing a one. In this paper, we propose a new scheduling policy, write power asymmetry scheduling (WPAS), that exploits the asymmetry of write power. WPAS improveswrite commands parallelism of PCM memory without violating power constraint. The evaluation results show that WPAS can improve performance by up to 35.5%, and 18.5% on average. The effective read latency can be reduced by up to 33.0%, and 17.1% on average.     

内存体系划分技术的研究与发展

在多核计算机时代,多道程序在整个共享内存体系上的“访存干扰”是制约系统总体性能和服务质量的重要因素.即使当前内存资源已相对丰富,但如何优化内存体系的性能、降低访存干扰并高效地管理内存资源,仍是计算机体系结构领域的研究热点.为深入研究该问题,详述将“页着色(pagecoloring)”内存划分技术应用于整个内存体系(包括Cache、内存通道以及内存DRAM Bank),进而消除了并行多道程序在共享内存体系上的访存干扰的一系列先进方法.从DRAM Bank、Channel与Cache以及非易失性内存(non-volatile memory, NVM)等内存体系中介质为切入点,层次分明地展开论述:首先,详述将页着色应用于多道程序在DRAM Bank与通道的划分,消除多道程序间的访存冲突;随后是将页着色应用于在内存体系中Cache和DRAM的“垂直”协同划分,可同时消除多级内存介质上的访存干扰;最后是将页着色应用于包含NVM的混合内存体系,以提高程序运行效率和系统整体效能.实验结果表明,所提内存划分方法提高了系统整体性能(平均5%-15%)、服务质量(QoS),并有效地降低了系统能耗.通过梳理...     

A hybrid memory built by SSD and DRAM to support in-memory Big Data analytics

Big Data requires a shift in traditional computing architecture. The in-memory computing is a new paradigm for Big Data analytics. However, DRAM-based main memory is neither cost-effective nor energy-effective. This work combines flash-based solid state drive (SSD) and DRAM together to build a hybrid memory, which meets both of the two requirements. As the latency of SSD is much higher than that of DRAM, the hybrid architecture should guarantee that most requests are served by DRAM rather than by SSD. Accordingly, we take two measures to enhance the hit ratio of DRAM. First, the hybrid memory employs an adaptive prefetching mechanism to guarantee that data have already been prepared in DRAM before they are demanded. Second, the DRAM employs a novel replacement policy to give higher priority to replace data that are easy to be prefetched because these data can be served by prefetching once they are demanded once again. On the contrary, the data that are hard to be prefetched are protected by DRAM. The prefetching mechanism and replacement policy employed by the hybrid memory rely on access patterns of files. So, we propose a novel pattern recognition method by improving the LZ data compression algorithm to detect access patterns. We evaluate our proposals via prototype and trace-driven simulations. Experimental results demonstrate that the hybrid memory is able to extend the DRAM by more than twice.