Optical homodyne receiver based on an improved balance phase-lockedloop with the date-to-phaselock crosstalk suppression

An improved balanced phase-locked loop (PLL) with postdetection processing is proposed to eliminate the data-to-phaselock crosstalk which potentially limits the usable ratio of laser linewidth to bit rate in pilot-carrier phase-shift keying (PSK) optical homodyne systems. The phase-lock current is first subtracted from the output signal of the data receiver before input to the loop filter. An attenuator is used to ensure the equilibrium of the feedback output signal and data-to-phaselock crosstalk. A shaping filter is introduced to simulate the distortion of data signals at the output of the preamplifier. The homodyne receivers based on this kind of PLL have the advantage of a large tolerance for the laser linewidth compared with the conventional balanced PLL receivers     

PSK optical homodyne detection using external cavity laser diodesin Costas loop

5-Gb/s optical PSK (phase-shift keying) homodyne detection experiments are discussed. In these experiments, the optical carrier is recovered by a Costas optical phase-locked loop using a multielectrode local oscillator (DFB) laser diode at 1.55 μm with a flat FM response. Although the beat linewidth of 80 kHz is broad compared to the loops in other phase-locked loop (PLL) experiments, phase locking with Costas loop is confirmed at 5 Gb/s by increasing the loop natural frequency. The receiver sensitivity is -42.2 dBm or 93 photon/bit for a 2⁷-1 pseudorandom bit sequence (PRBS) in front of a 90° hydride     

A new lock indicator circuit for microwave and millimeter-wavephase locked loops

A circuit useful as a lock detector in microwave phase-locked loop (PLL) systems has been developed. This circuit avoids the quadrature phase detector or coherent amplitude detector commonly used as a lock indicator in PLLS, thereby reducing the microwave circuitry and components. It is based on the properties of the phase-error signal coming from the phase detector; a frequency-voltage conversion is performed on it in a low-frequency (secondary) PLL, the input to which is the output of the phase detector in the main (microwave) PLL. The secondary voltage-controlled oscillator (VCO) control signal gives, after a comparison, a logic level related to the lock condition in the main (microwave) PLL. This circuit has been used with success in microwave phase-locked oscillators (PLOs) in which the phase detection was made at 290 MHz, 2.55 GHz, 27 GHz and 29.7 GHz     

An all-digital bit detector for compact disc players

A bit detector is described which is suitable for integration using digital VLSI technology. In the bit detector the signal is sampled at a fixed clock frequency which is not related to the bit rate of the input signal. The incoming bits are detected by comparing the digitized input signal with the output of an all-digital phase-locked loop (PLL), which regenerates the bit clock that is present in the input signal. The design must be sufficiently robust to handle deviations in the physical size of the pits and disturbances like dropouts. Experimental optimization of the bit detector was performed with the aid of a hardware realization     

Performance of PLL Synchronized Optical PPM Communication Systems

Receiver timing synchronization of an optical PPM communication system can be achieved using a phase-locked loop (PLL) if the photodetector output is properly processed. The synchronization performance is shown to improve with increasing signal power and decreasing loop bandwidth. The bit error rate performance of the PLL synchronized PPM system is analyzed and compared to that of the perfectly synchronized system. It is shown that the increase in signal power needed to compensate for the imperfect synchronization is small (less than 0.1 dB) for loop bandwidths less than 0.1 percent of the slot frequency.     

Decision-directed PLL for coherent optical pulse CDMA systems inthe presence of multiuser interference, laser phase noise, and shotnoise

A digital decision-directed phase-locked loop (PLL) for use in optical pulse code-division multiple-access (CDMA) systems based on coherent correlation demodulation is proposed. PLL performance is affected by multiuser interference, laser phase noise and optical shot noise. The effect of these sources of interference and noise on PLL performance is evaluated based on a nonlinear model (the Fokker-Planck method) since a linear analysis yields large deviations between the analytical results and actual performance at low signal-to-noise ratios (SNRs). After describing the implementation of the PLL, the steady-state probability density function (pdf) of the phase estimator is derived. Numerical evaluation of the variance of the phase estimator is given for Gold codes. The linewidth requirements of the laser for an acceptable phase estimator variance and the value of the optimal loop bandwidth minimizing the impact of the interference and noise on the PLL are discussed     

10-GHz clock recovery using an optoelectronic phase-locked loop based on three-wave mixing in periodically poled lithium niobate

Clock recovery is a critical function of any digital communications system. To replace the classical electronic phase-locked loops (PLLs) at higher bit rates, several all-optical or optoelectronic clock recovery methods are being studied. This letter presents an optoelectronic PLL where three-wave mixing in a periodically poled lithium niobate (PPLN) device provides the phase comparator. Since PPLN is passive, it generates no amplified spontaneous emission noise; also, the error signal is in the visible (763 nm), therefore easily separated from infrared input signals. Clock recovery is performed on a 10-GHz sinusoidal optical signal. Being based on ultrafast nonlinear effects, this scheme should be able to reach still higher bit rates, on the order of several hundred gigahertz. Also, subclock extraction (e.g., 40-to-10 GHz) should be possible without modifications.     

锁相环工作原理及仿真分析

为了探究锁相环的工作本质,在构建数学模型的基础上,求出了环路的相位误差响应,并利用零输入和零状态响应的含义引申出环路的工作性能.从定量与定性两方面说明了锁相环既可调频又可调相的实质.接着,为了更进一步加深理解,又从电荷泵锁相环的角度,介绍了原理,并用仿真实例加以验证.从而说明,当进行频道转换时,环路首先进行调频,即粗调...     

注入锁定对激光锁相环性能的影响

本文研究了注入锁定对半导体激光锁相环性能的影响,给出了注入锁定半导体激光器作为激光锁相环本振的相位传递函数及激光锁相环的噪声特性.     

Application of a PLL and ALL noise reduction process in opticalsensing systems

A novel approach to the demodulation of a frequency modulated optical signal using an amplitude-locked loop (ALL) in the presence of noise is presented. The ALL is the mathematical dual of the phase-locked loop (PLL), but works on amplitude rather than phase. This technique will benefit areas where noise due to scattering or multiple reflections is present     

Phase Lock for Correlation Detection of a Periodic Pulse

The detection of the presence of a periodic pulse with uncertain pulse rate and low duty cycle is a common biotelemetry problem. Modern phase-lock and correlation techniques have provided more efficient means of making the presence decision than that provided by energy detection methods. A local signal is cross correlated with the input in a phase-locked loop (PLL) to provide phase reference. Upon lock, a local duplicate signal is generated and correlated with the input. A decision threshold operates on the correlator output. The PLL with filter F(s) = (s+a)/s and three appropriate nonlinearities are analyzed for acquisition time and maximum frequency error that will lock.     

The Optimum Closed-Loop Transfer Function of a Phase-Locked Loop Used for Synchronization Purposes

This paper presents an expression for the optimum closed-loop transfer function of a phase-locked loop (PLL) which estimates the phase of an unmodulated sinuosoid corrupted by an additive random disturbance. This matter has been extensively treated (e.g., [1, ch. 4]) in the conventional PLL theory, where the disturbance is a stationary noise process. However, for an important class of synchronizers operating on a PAM waveform corrupted by stationary noise, the disturbance at the input of the PLL cannot be treated as a stationary process. In this case we show that the PLL transfer function which is optimized according to the conventional PLL theory is far from optimum. Therefore, we derive the closed-loop transfer function which is optimum for a more general disturbance. This extension of the conventional PLL theory applies to most synchronizers.     

Frequency-Offset PLL for Synchronous Optical Sampling of OTDM Signals

We demonstrate a novel synchronization scheme for optical sampling which is based on a nonstandard phase-locked loop (PLL). Phase comparison is performed at a 10-GHz optical time-division-multiplexing (OTDM) base rate, thus avoiding ultrafast detectors and electronics. The employed frequency-offset PLL allows synchronous sampling of OTDM signals (or any other signals with bit rates given by integer multiples of the base rate), which would be impossible using a standard PLL. This provides a higher degree of flexibility for problem-specific sweeping than asynchronous sampling     

A 155-MHz clock recovery delay- and phase-locked loop

The authors describe a completely monolithic delay-locked loop (DLL) that may be used either by itself as a deskewing element, or in conjunction with an external voltage-controlled crystal oscillator (VCXO) to form a delay- and phase-locked loop (D/PLL). By phase shifting the input data rather than the clock, the DLL and D/PLL provide jitter-peaking-free clock recovery. Additionally, the jitter transfer function of the D/PLL has a low bandwidth for good jitter filtering without compromising acquisition speed. The D/PLL described here exhibits less than 1° r.m.s. jitter on the recovered clock, independent of the input data density. No jitter peaking is observed over the 40-kHz jitter bandwidth     

基于半速率锁相环的5Gb/s CMOS单片时钟恢复电路

利用TSMC的O．18μm CMOS工艺,设计实现了单片集成的5 Gb/s锁相环型时钟恢复电路。该电路采用由半速率鉴相器、四相位环形电流控制振荡器、电荷泵以及环路滤波器组成的半速率锁相环结构。测试表明：在输入速率为5 Gb/s、长度为211-1伪随机序列的情况下,恢复出时钟的均方根抖动为4．7 ps。在偏离中心频率6MHz频率处的单边带相位噪声为-112．3 dBe/Hz。芯片面积仅为0．6mm×O．6 mm,采用1.8 V电源供电,功耗低于90 mW。     

C波段锁相变频器模块

设计了一种采用锁相环技术的C波段变频器模块,其原理是输入的信号与压控振荡器(VCO)信号相混频,产生两个信号频率差的信号,这个信号与差频信号IF进行鉴频鉴相,产生的误差信号经环路滤波送入压控振荡器(VCO)的调谐端完成锁相,这时压控振荡器输出的信号就是需要的信号。采用这种技术,模块输出的有用信号与输入信号泄漏到输出端口的功率比在83dB以上,可以达到较好的效果,同时可有效避免使用体积较大的腔体带通滤波器。     

一种应用于阵列TDC的低抖动锁相环设计

传统的PLL（Phase Locked Loop）电路受限于环路参数的选定,其相位噪声与抖动特性已经难以满足大阵列、高精度TDC（Time-to-Digital Converter）的应用需求.本文致力于PLL环路带宽的优化选取,采取TSMC 0.35μm CMOS工艺实现了一款应用于TDC的具有低抖动、低噪声特性的锁相环（Phase Locked Loop,PLL）电路,芯片面积约为0.745mm×0.368mm.实际测试结果表明,在外部信号源输入15.625MHz时钟信号的条件下,PLL输出频率可锁定在250.0007MHz,频率偏差为0.7kHz,输出时钟占空比为51.59%,相位噪声为114.66dBc/Hz@1MHz,均方根抖动为4.3ps,峰峰值抖动为32.2ps.锁相环的相位噪声显著降低,输出时钟的抖动特性明显优化,可满足高精度阵列TDC的应用需要.     

Phase modulation of a loop phase-locked grid oscillator array

In this letter, we describe a method for phase modulation of a loop phase-locked grid oscillator array and report results obtained in a test bed implementation of the method. The key to the scheme lies in introducing the phase-locked loop (PLL) in such a way that the modulating data stream is introduced in parallel with the loop rather than through it, thereby circumventing the bandwidth limitation of the PLL. The experiment was performed at 4.7 GHz with a phase-locked grid oscillator array. The grid oscillator was successfully modulated by a 1 MHz signal, which is ten times higher than the bandwidth of the phase-locked loop     

10 GHz full-rate clock and data recovery circuit in 0.18 /spl mu/m CMOS without external reference clock

The design of a fully monolithic integrated 10 GHz full-rate clock and data recovery (CDR) circuit in 0.18 /spl mu/m digital CMOS technology, which employs an injection phase-locked loop (PLL) technique is presented. The CDR operating without the external reference exhibits a capture range of 200 MHz while consuming 205 mA current from 1.8 V supply including the output buffer. The recovered clock signal with 250 mV/sub pp/ pseudorandom bit Sequence input data of length 2/sup 31/-1 exhibits 7.9 ps of peak-to-peak (p-p) and 1.1 ps of root-mean-square (RMS) jitter. The measured clock phase noise at 1 MHz offset is approximately -109 dBc/Hz.     

Damping factor influence on linewidth requirements for optical PSKcoherent detection systems

Spectral linewidth requirements for optical phase-shift-keying (PSK) coherent detection systems are found to depend on the phase-locked loop (PLL) parameters. Until now, the damping factor of the PLL has been assumed to be 1/√2 when deriving the required spectral linewidth of a light source, because it is at this value that an electrical PLL offers near optimum performance in many cases. By increasing the PLL damping factor above 1/√2, it is shown that there exists a maximum value of the required linewidth that achieves a received optical power penalty of 1 dB at a bit error rate of 10^-10. The required beat linewidths so obtained are 50% larger than previously reported results (which assume a damping factor of 1/√2). As for PLL frequency acquisition performance, it is shown that raising the camping factor above 1/√2 does not seriously affect the hold-in limit or the pull-in limit. It is also shown that the normalized loop gain that optimizes PLL performance is roughly one half the normalized loop gain at which the PLL oscillation commences