低复杂度FIR数字滤波器设计方法

FIR滤波器具有绝对稳定性和线性相位的优势,然而当对滤波器的频域性能要求较高时,FIR滤波器通常需要很高的阶数,这使得FIR滤波器硬件执行的复杂度很高。为降低FIR滤波器的硬件执行复杂度,诸多研究者进行了探索。文章对低复杂度FIR滤波器设计方法进行研究,着重介绍比较典型的频率响应罩设计方法、外插脉冲响应设计方法和基于压缩感知的设计方法。     

基于FPGA的FIR数字滤波器的优化设计

提出采用正则有符号数字量（CSD）编码技术实现FIR滤波器。首先分析了FIR数字滤波器理论及常用设计方法的不足,然后介绍了二进制数的CSD编码技术及其特点,给出了其于CSD编码的定点常系数FIR滤波器设计过程,使用VHDI,语言实现了该常系数滤波器的行为描述。最后在Max＋PlusⅡ环境下进行实验仿真和验证,与DA和2C编码算法比较结果表明,用CSD编码技术实现的滤波器可以有效提高运算速度并降低FPGA芯片的面积占用。     

改进型主成份分析外插脉冲响应滤波器设计

外插脉冲响应(EIR)滤波器设计技术是一种低复杂度有限冲击响应(FIR)滤波器设计技术,而基于主成份分析(PCA)的EIR(PCA-EIR)滤波器设计技术是一种有效(算法执行简单,效果较好)的EIR滤波器设计技术.PCA-EIR技术通过对由原型FIR滤波器系数组成的系数矩阵采用PCA技术进行降维来近似合成原型FIR滤波器,以达到降低原型滤波器硬件执行复杂度的目的.本文提出了一种简单有效的改进型PCA-EIR技术,其基本思想是将系数矩阵的前若干列向量保持不变,对剩余部分列向量组成的矩阵采用PCA技术进行降维来合成原型FIR滤波器.所提出改进型PCA-EIR技术的算法执行复杂度与传统PCA-EIR技术相当,且在滤波器频率响应指标基本相等的前提下,改进型PCA-EIR技术节省3.5％-17.5％乘法器和25.6％-51.6％加法器,从而进一步降低了FIR滤波器的硬件执行复杂度.     

FIR滤波器的FPGA高效实现和巧妙验证

为了降低FIR滤波器对FPGA资源的消耗,同时能够直接验证其滤波性能,本文介绍了基于加法器网络的FIR滤波器的实现方法,以及系数的CSD码、最优CSD码表示方法,并引出了更加高效的简化加法器网络法.以一个32阶FIR低通滤波器的实现为例说明了设计的过程,巧妙结合MATALB与QuartusⅡ对所设计的滤波器进行了验证.实践表明,该方法节约资源,调试方便.     

基于FPGA的FIR滤波器高效实现

本文针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行研究,首先给出了将乘法转化为查表的DA算法,然后简要介绍整数的CSD表示和我们根据FPGA实现要求改进的最优表示;接着,本文讨论了在离散系数空间得到FIR滤波器系数最优解的混合整数规划方法;最后采用这一方法设计了最优表示离散系数FIR滤波器,通过FPGA仿真验证这一方法是可行的和高效的.     

基于FRM结构的FIR滤波器的采样率变换方法

该文在分析滤波器传递函数的对称性与其冲激响应的关系的基础上,提出了一类具有稀疏冲激响应系数的特殊滤波器,以这类滤波器作为原型滤波器可以进一步降低FRM结构FIR滤波器的计算复杂度。并研究了基于此类FRM结构FIR滤波器的采样率变换算法、实现结构、计算复杂度及其设计问题等。最后,通过实际例子验证这种采样率变换方法的有效性。     

基于FPGA的高效FIR滤波器设计与实现

给出了一种基于FPGA的数字滤波器的设计方法.该方法先通过MATLAB设计出一个具有具体指标FIR滤波器,再对滤波器系数进行处理,使之便于在FPGA中实现,然后采用基于分布式算法和CSD编码的滤波器结构进行设计,从而避免了乘法运算,节约了硬件资源,其流水线的设计方式也提高了运行速度.Matlab和Modelsim防真表明,该设计功能正确,能实现快速滤波     

基于可重构FPGA技术的自适应FIR滤波器的实现

有限冲激响应(FIR)滤波器设计遇到的难题是滤波要进行大量乘法运算,即使是在全定制的专用集成电路中也会导致过大的面积与功耗.对于用硬件实现系数是常量的专用滤波器,可以通过分解系数变为应用加、减和移位而实现乘法.FIR滤波器的复杂性主要由用于系数乘法的加法器/减法器的数量决定.而对于自适应FIR滤波器,大多数场合下可用数字信号处理器(DSP)或CPU通过软件编程的方法来实现,但是对于要求高速运算的场合,VLSI实现是很好的选择.基于这一考虑,可以用符号数的正则表示(CSD)码表示系数, 再利用可重构现场可编程门阵列(FPGA)技术实现.可重构结构的应用,能保证系统的其余部分同时处于运行状态时实现FIR滤波器系数的更新.文中利用CSD码和可重构思想,提出了用FPGA实现自适应FIR滤波器的一种方案.     

用于太赫兹高速通信的FIR滤波器64并行实现算法

为满足太赫兹无线通信系统对大容量基带信号处理算法的要求,基于直接从多项式分解导出的传统滤波器并行实现算法,通过矩阵变化推导出复杂度更小的快速有限冲激响应(FIR)滤波器并行实现。在此基础上通过张量积的表示给出了2并行、4并行和8并行的转换公式以及实现架构。既而推导出2N并行快速FIR滤波器的通用实现公式,并对比了优化前后的复杂度差异。最后给出了64并行的快速FIR滤波器的推导公式和具体实现架构,以及优化前后的硬件复杂度对比,64并行的快速FIR滤波器算法资源消耗更少。     

FPGA实现FIR抽取滤波器的设计

采用基于分布式算法思想的方法来设计FIR滤波器,利用FDAtool设计系统参数,计算滤波器系数,同时为了要满足系统要求考虑系数的位数。根据FIR数字滤波器结构,对FIR数字滤波器的FPGA实现方法进行分析。     

Low-Area/Power Parallel FIR Digital Filter Implementations

This paper presents a novel approach for implementing area-efficient parallel (block) finite impulse response (FIR) filters that require less hardware than traditional block FIR filter implementations. Parallel processing is a powerful technique because it can be used to increase the throughput of a FIR filter or reduce the power consumption of a FIR filter. However, a traditional block filter implementation causes a linear increase in the hardware cost (area) by a factor of L, the block size. In many design situations, this large hardware penalty cannot be tolerated. Therefore, it is important to design parallel FIR filter structures that require less area than traditional block FIR filtering structures. In this paper, we propose a method to design parallel FIR filter structures that require a less-than-linear increase in the hardware cost. A novel adjacent coefficient sharing based sub-structure sharing technique is introduced and used to reduce the hardware cost of parallel FIR filters. A novel coefficient quantization technique, referred to as a scalable maximum absolute difference (MAD) quantization process, is introduced and used to produce quantized filters with good spectrum characteristics. By using a combination of fast FIR filtering algorithms, a novel coefficient quantization process and area reduction techniques, we show that parallel FIR filters can be implemented with up to a 45% reduction in hardware compared to traditional parallel FIR filters.     

Design of High-Order Extrapolated Impulse Response FIR Filters with Signed Powers-of-Two Coefficients

Expensive multiplication operations can be replaced by simpler additions and hardwired shifters so as to reduce power consumption and area size, if the coefficients of a digital filter are signed power-of-two (SPT). As a consequence, FIR digital filters with SPT coefficients have been widely studied in the last three decades. However, most approaches for the design of FIR filters with SPT coefficients focus on filters with length less than 100. These approaches are not suitable for the design of high-order filters because they require excessive computation time. In this paper, an approach for the design of high-order filters with SPT coefficients is proposed. It is a two-step approach. Firstly, the design of an extrapolated impulse response (EIR) filter is formulated as a standard second-order cone programming (SOCP) problem with an additional coefficient sensitivity constraint for optimizing its finite word-length effect. Secondly, the obtained continuous coefficients are quantized into SPT coefficients by recasting the filter-design problem into a weighted least squares (WLS) sequential quadratic programming relaxation (SQPR) problem. To further reduce implementation complexity, a graph-based common subexpression elimination (CSE) algorithm is utilized to extract common subexpressions between SPT coefficients. Simulation results show that the proposed method can effectively and efficiently design high-order SPT filters, including Hilbert transformers and half-band filters with SPT coefficients. Experiment results indicate that 0.81N∼0.29N adders are required for 18-bit N-order FIR filters (N=335∼3261) to meet the given magnitude response specifications.     

Quantization of FIR filters under a total integer cost constraint

In this paper, we present computationally efficient algorithms for obtaining a particular class of optimal quantized representations of finite-impulse response (FIR) filters. We consider a scenario where each quantization level is associated with a certain integer cost and, given an FIR filter with real coefficients, our goal is to find the quantized representation that minimizes a certain error criterion under a constraint on the total cost of all quantization levels used to represent the filter coefficients. We first formulate the problem as a constrained shortest path problem and discuss how an efficient dynamic programming algorithm can be used to obtain the optimal quantized representation for arbitrary quantization sets. We then develop a greedy algorithm which has even lower computational complexity and is shown to be optimal when the quantization levels and their associated costs satisfy a certain, easily checkable criterion. For the special case of the quantization set that involves levels that are sums of signed powers-of-two and whose cost is captured by the number of powers of two used in their representation, the total integer cost relates to the cost of the very large-scale integration implementation of the given FIR filter and our analysis clarifies the optimality of previously proposed algorithms in this setting.     

CSDC: a new complexity reduction technique for multiplierless implementation of digital FIR filters

We present a computation reduction technique called computation sharing differential coefficient (CSDC) method, which can be used to obtain low-complexity multiplierless implementation of finite-impulse response (FIR) filters. It is also applicable to digital signal processing tasks involving multiplications with a set of constants. The main component of our proposed CSDC method is to combine the strength of the augmented differential coefficient approach and subexpression sharing. Exploring computation reuse through algorithmic equivalence, the augmented differential coefficient approach greatly expands the design space by employing both differences and sums of filter coefficients. The expanded design space is represented by an undirected and complete graph. The problem of minimizing the adder cost (the number of additions/subtractions) for a given filter is transformed into a problem of searching for an appropriate subexpression set that leads to a minimal adder cost. A heuristic search algorithm based on genetic algorithm is developed to search for low-complexity solutions over the expanded design space in conjunction with exploring subexpression sharing. It is shown that up to 70.1% reduction in the adder cost can be obtained over the conventional multiplierless implementation. Comparison with several existing techniques based on the available data shows that our method yields comparable results for multiplierless FIR filter implementation.     

Hardware-efficient FIR filters with reduced adder step

A technique for reducing the hardware complexity of constant coefficient finite impulse response (FIR) digital filters, without increasing the number of adder steps in the multiplier block adders, is presented. The filter coefficients are adjusted so that the number of full adders in the hardware implementation of any coefficient is independent of the coefficient wordlength and the number of shifts between nonzero bits in the coefficient. Results show that the proposed technique achieves a significant reduction in both the multiplier block adders and the multiplier block full adders when compared to existing techniques.     

A programmable FIR digital filter using CSD coefficients

An area-efficient programmable FIR digital filter using canonic signed-digit (CSD) coefficients was implemented that uses a switchable unit-delay to allocate the desired number of nonzero CSD coefficient digits to each filter tap. The prototype chip can allocate up to 16 pairs of nonzero CSD coefficient digits for a linear-phase filter, thus realizing filters with 32 linear-phase taps operating at 180 MHz with two nonzero CSD digits per filter tap. Additional nonzero CSD digits can be allocated to filter taps at the penalty of a reduced filter length and a reduced data-rate. The chip was implemented with 16-bit I/O in a die size of 5.9 mm by 3.4 mm using 1.0-μm CMOS technology     

Design and hybrid realization of FIR Nyquist filters with quantized coefficients and low sensitivity to timing jitter

A design of finite impulse response (FIR) Nyquist filters with zero intersymbol interference (ISI) and low sensitivity to timing jitter is presented. Using an affine scaling linear programming algorithm, a near-optimum quantized coefficient set can be obtained in a feasible computational time. By varying a parameter, the design provides a tradeoff between the tail energy of the impulse response in the time domain and the stopband of the magnitude response in the frequency domain. We also present a pipelined multiplier-free FIR filter realization with periodically time-varying (PTV) coefficients based on a hybrid form. The realizations exploit the coefficient symmetry to reduce the hardware by about one half. By placing most of the shifts followed by addition toward the back end of the structure, hardware is reduced due to the shorter wordlength of the adders. The proposed structure has a provision to increase the speed by adjusting a design parameter but at the expense of more hardware.     

An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth

It is well known that common subexpression elimination techniques minimize the two main cost metrics namely logic operators and logic depths in realizing finite impulse response (FIR) filters. Two classes of common subexpressions occur in the canonic signed digit representation of filter coefficients, called the horizontal and the vertical subexpressions. Previous works have not addressed the trade-offs in using these two types of subexpressions on the logic depth and the number of logic operators of coefficient multipliers. In this paper, we analyze the impact of the horizontal and the vertical common subexpression elimination techniques on reducing the logic depth and number of logic operators in FIR filters. Further, we present an algorithm to optimize the common subexpression elimination that produces FIR filters with fewer numbers of logic operators when compared with other common subexpression elimination algorithms in literature. The design examples show that the average reduction of logic operators achieved using our method over the weight-2 horizontal common subexpression elimination method which produced the best trade-off between logic operators and logic depth (contention resolution algorithm, CRA-2 [F. Xu, C.-H. Chang, C.-C. Jong, Contention resolution algorithm for common subexpression elimination in digital filter design, IEEE Trans. Circuit Syst. II 52(10) (2005) 695-700 (October)]) is 15%. This reduction of logic operators is achieved without any increase in the logic depth. When compared with the recently proposed multiple adder graph (MAG) algorithm [Jeong-Ho Han, In-Cheol Park, FIR filter synthesis considering multiple adder graphs for a coefficient, IEEE Trans. Comput.-Aid. Design Integ. Circuit Syst. 27(5) (2008) 958-962 (May)], the average reduction of logic operators obtained using our method is 5% and the reduction of logic depth is 25%.     

Pipelined array-based FIR filter folding

The elaborate design of folded finite-impulse response (FIR) filters based on pipelined multiplier arrays is presented in this paper. The design is considered at the bit-level and the internal delays of the pipelined multiplier array are fully exploited in order to reduce hardware complexity. Both direct and transposed FIR filter forms are considered. The carry-save and the carry-propagate multiplier arrays are studied for the filter implementations. Partially folded architectures are also proposed which are implemented by cascading a number of folded FIR filters. The proposed schemes are compared as to the aspect of hardware complexity with a straightforward implementation of a folded FIR filter based on the pipelined Wallace Tree multiplier. The comparison reveals that the proposed schemes require 20%-30% less hardware. Finally, efficient implementation of partially folded FIR filter circuits is presented when constraints in area, power consumption and clock frequency are given.