High-gain transimpedance amplifier in InP-based HBT technology forthe receiver in 40-Gb/s optical-fiber TDM links

A monolithic integrated transimpedance amplifier for the receiver in a 40-Gb/s optical-fiber TDM system has been fabricated in an InP-based HBT technology. Despite its high gain (transimpedance of 2 kΩ in the limiting mode, 10 kΩ in the linear mode) the complete amplifier was realized on a single chip. Clear output eye diagrams were measured up to 43 Gb/s under realistic driving conditions. The voltage swing of 0.6 V_pp at the differential 50 Ω output does not change within the demanded input dynamic range of 6 dB. At the upper input current level even 48 Gb/s were achieved. The power consumption is approximately 600 mW at a single supply voltage of -5.5 V     

A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBTlimiting amplifier

A limiting amplifier IC implemented in a silicon-germanium (SiGe) heterojunction bipolar transistor technology for low-cost 10-Gb/s applications is described. The IC employs 20 dB gain limiting cells, input overload protection, split analog-digital grounds, and on-chip isolation interface with transmission lines. A gain enhancement technique has been developed for a parallel-feedback limiting cell. The limiting amplifier sensitivity is less than 3.5 mV_pp at BER=10^-9 with 2-V_pp maximum input (55-dB dynamic range). The total gain is over 60 dB, and S₂₁ bandwidth exceeds 15 GHz at 10-mV_pp input. Parameters S₁₁ and S₂₂ are better than -10 dB in the 10-GHz frequency range. The AM to PM conversion is less than 5 ps across input dynamic range. The output differential voltage can be set from 0.2 to 2 V_pp with IC power dissipation from 250 mW to 1.1 W. The chip area is 1.2×2.6 mm². A 10-Gb/s optical receiver, built with the packaged limiting amplifier, demonstrated -19.6-dBm sensitivity. The IC can be used in 10-Gb/s fiber-optic receivers requiring high sensitivity and wide input dynamic range     

Analysis, design, and optimization of InGaP-GaAs HBTmatched-impedance wide-band amplifiers with multiple feedback loops

The realization of matched impedance wide-band amplifiers fabricated by InGaP-GaAs heterojunction bipolar transistor (HBT) process is reported. The technique of multiple feedback loops was used to achieve terminal impedance matching and wide bandwidth simultaneously. The experimental results showed that a small signal gain of 16 dB and a 3-dB bandwidth of 11.6 GHz with in-band input/output return loss less than -10 dB were obtained. These values agreed well with those predicted from the analytic expressions that we derived for voltage gain, transimpedance gain, bandwidth, and input and output impedances. A general method for the determination of frequency responses of input/output return losses (or S₁₁, S₂₂) from the poles of voltage gain was proposed. The intrinsic overdamped characteristic of this amplifier was proved and emitter capacitive peaking was used to remedy this problem. The tradeoff between the input impedance matching and bandwidth was also found     

5 V, DC-12 GHz InP/InGaAs HBT amplifier

An InP/InGaAs HBT cascode amplifier operating from a single 5 V power supply is described. The circuit has a DC gain of 17.2 dB and a -3 dB frequency point of 12.3 GHz. This results in a gain-bandwidth product in excess of 90 GHz. The frequency response of the amplifier remains constant if the power supply voltage is as low as 4 V.<>     

Linearised InGaP/GaAs HBT MMIC power amplifier with active biascircuit for W-CDMA application

A high linearity InGaP/GaAs heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (MMIC) power amplifier is demonstrated using a new structure for a bias circuit for wideband-code division multiple access (W-CDMA) application. A one shunt capacitor is added to a novel active bias circuit and acts as a lineariser improving input P_{1 dB} of 16 dB and phase distortion of 5.1° for the hybrid phase shift keying (HPSK) modulated signal at the 28 dBm output power; the lineariser showing no significant increase of signal loss and chip area. The two-stage HBT MMIC amplifier exhibits a power-added efficiency (PAE) of 37%, a linear power gain of 24.5 dB, and an output power of 28 dBm with an adjacent channel power ratio (ACPR) of -45 dBc, under a 3 V operation voltage     

低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

2.5 dB NF 3.1-10.6 GHz CMOS UWB LNA with small group-delay variation

A 3.1-10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay variation is only plusmn 16.7 ps across the whole band) using standard 0.13 mum CMOS technology is reported. To achieve high and flat gain and small group-delay variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA achieved input return loss (S₁₁) of -17.5 to -33.6 dB, output return loss (S₂₂) of -14.4 to -16.3 dB, flat forward gain (S₂₂) of 7.92 plusmn 0.23 dB, and reverse isolation (S₁₂) of -25.8 to -41.9 dB over the 3.1-10.6 GHz band of interest. A state-of-the-art noise figure (NF) of 2.5 dB was achieved at 10.5 GHz.     

A 44-GHz-high IP3 InP HBT MMIC amplifier for low DC powermillimeter-wave receiver applications

This paper reports on what is believed to be the highest IP3/P_dc power linearity figure of merit achieved from a monolithic microwave integrated circuit (MMIC) amplifier at millimeter-wave frequencies. The 44 GHz amplifier is based on an InP heterojunction bipolar transistor (HBT) technology with f_T's and f_max's of 70 and 200 GHz, respectively. The 44-GHz amplifier design consists of four prematched 1×l0μm² four-finger (40-μm²) heterojunction bipolar transistor (HBT) cells combined in parallel using a compact λ/8 four-way microstrip combiner. Over a 44-50-GHz frequency band, the amplifier obtains a gain of 5.5-6 dB and a peak gain of 6.8-7.6 dB under optimum gain bias. At a low bias current of 48 mA and a total dc power of 120 mW, the amplifier obtains a peak IP3 of 34 dBm, which corresponds to an IP3/P_dc power ratio of 21:1, a factor of two better than previous state-of-the-art MMIC's reported in this frequency range. By employing a thin, lightly doped HBT collector epitaxy design tailored for lower voltage and higher IP3, a record IP3/P_dc, power ratio of 42.4:1 was also obtained and is believed to be the highest reported for an MMIC amplifier of any technology. The new high-linearity HBT's have strong implications for millimeter-wave receiver as well as low-voltage wireless applications     

A DC-20-GHz InP HBT balanced analog multiplier for high-data-ratedirect-digital modulation and fiber-optic receiver applications

This paper reports on a dc-20-GHz InP heterojunction bipolar transistor (HBT) active mixer, which obtains the highest gain-bandwidth product (GBP) thus far reported for a direct-coupled analog mixer integrated circuit (IC). The InP HBT active mixer is based on the Gilbert transconductance multiplier cell and integrates RF, local oscillator, and IF amplifiers, High-speed 70-GHz f_T and 160-GHz f_max InP HBT devices along with microwave matching accounts for its record performance. Operated as a down-converter mixer, the monolithic microwave integrated circuit achieves an RF bandwidth (BW) from dc-20 GHz with 15.3-dB gain and benchmarks a factor of two improvement in GBP over state-of-the-art analog mixer ICs. Operated as an up-converter, direct-digital modulation of a 2.4-Gb/s 2³¹ -1 pseudorandom bit sequence (PRBS) onto a 20-GHz carrier frequency resulted in a carrier rejection of a 28 dB, clock suppression of 35 dBc, and less than a 50-ps demodulated eye phase jitter. The analog multiplier was also operated as a variable gain amplifier, which obtained 20-dB gain with a BW from dc-18 GHz, an third-order intercept of 12 dBm, and over 25 dB of dynamic range. A single-ended peak-to-peak output voltage of 600 mV was obtained with a ±35-mV 15 Gb/s 2⁵-1 PRES input demonstrating feasibility for OC-192 fiber-telecommunication data rates. The InP-based analog multiplier IC is an attractive building block for several wideband communications such as those employed in satellites, local multipoint distribution systems, high-speed local area networks, and fiber-optic links     

一种自适应线性化偏置的单片集成功率放大器

提出一种自适应线性化偏置的电路结构,通过调节控制电压改变偏置管的工作状态,提高功率放大电路的线性度,降低偏置电流对参考电压和环境温度的敏感度.利用双反馈环结构抑制输入阻抗随频率的变化,实现了宽带匹配,拓展了放大器的带宽.采用微波电路仿真软件AWR进行仿真,验证了带宽范围内的相位偏离度在2°以内.基于2μm InGaP/GaAs HBT工艺,设计了集成电路版图并成功流片.测试结果表明:在3.5V电压供电下,该放大器在1～2.5 GHz频带范围内,输入反射系数均在-10 dB以下,功率增益为23 dB,输出功率大于30 dBm,误差向量幅度在2.412 GHz时为.2.7％@24 dBm,最大功率附加效率达40％.     

应用于TD-SCDMA移动终端的单片InGaP/GaAs HBT功率放大器

报道了用于TD-SCDMA移动终端的高效率、高线性度HBT功率放大器的研制. 该单片功率放大器采用两级放大结构,内部集成了输入匹配、级间匹配网络以及有源偏置电路,总芯片面积仅为0.91mm×0.98mm. 该功率放大器采用单电源3.4V供电,在高、低功率模式下,PAE分别为43%和16%,增益达到了28.5以及24dB. 当输入QPSK调制信号时,在低输出功率以及高输出功率状态下,1.6MHz/3.2MHz中心频偏处,ACPR分别低于-45dBc/-56dBc 和-39dBc/-50dBc. 本芯片尺寸小,电压稳定性高,性能优越,为低成本化的大规模生产提供了可能性.     

Linearised HBT MMIC power amplifier with partially RF coupled active bias circuit for W-CDMA portable terminals applications

A highly linear MMIC power amplifier for wideband code-division multiple-access (W-CDMA) portable terminals has been devised and implemented with a new integrated on-chip lineariser. The proposed lineariser, consisting of an InGaP/GaAs heterojunction bipolar transistor (HBT) active bias circuit partially coupled to RF input power together with a feedback capacitor, effectively improves gain compression with little insertion power loss and no additional die area. The optimised lineariser improves maximum output power (P1 dB) by 2 dB and adjacent channel leakage power ratio (ACLR) by 4 dB, and the implemented HBT MMIC power amplifier exhibits a P1 dB of 30 dBm, a power gain of 30 dB, a power added efficiency of 42% at the maximum output power under an operation voltage of 3.4 V, and an ACLR of -34 dBc at 27 dBm of output power.     

Sound design of low power nested transconductance-capacitancecompensation amplifiers

An amplifier design approach is presented which is based on an all region MOS transistor model. Low power analogue circuits are designed using the presented approach. For illustrative purposes a nested transconductance-capacitance compensated (NGCC) operational amplifier is designed. Verification was carried out using a CMOS chip prototype which yields an op-amp with 105 dB gain, a 1.05 MHz gain-bandwidth product, 0.28 mW power consumption and 0.137 mm² active area for a 2 V supply voltage and 10 kΩ/20pF load     

A low-power and high-gain fully integrated CMOS LNA

In this paper, we present the design of a fully integrated CMOS low noise amplifier (LNA) with on-chip spiral inductors in 0.18 μm CMOS technology for 2.4 GHz frequency range. Using cascode configuration, lower power consumption with higher voltage and power gain are achieved. In this configuration, we managed to have a good trade off among low noise, high gain, and stability. Using common-gate (CG) configuration, we reduced the parasitic effects of C_gd and therefore alleviated the stability and linearity of the amplifier. This configuration provides more reverse isolation that is also important in LNA design. The LNA presented here offers a good noise performance. Complete simulation analysis of the circuit results in center frequency of 2.4 GHz, with 37.6 dB voltage gain, 2.3 dB noise figure (NF), 50 Ω input impedance, 450 MHz 3 dB power bandwidth, 11.2 dB power gain (S₂₁), high reverse isolation (S₁₂)<−60 dB, while dissipating 2.7 mW at 1.8 V power supply.     

A 23-dBm 60-GHz Distributed Active Transformer in a Silicon Process Technology

In this paper, a distributed active transformer for the operation in the millimeter-wave frequency range is presented. The transformer utilizes stacked coupled wires as opposed to slab inductors to achieve a high coupling factor of k_f=0.8 at 60 GHz. Scalable and compact equivalent-circuit models are used for the transformer design without the need for full-wave electromagnetic simulations. To demonstrate the feasibility of the millimeter-wave transformer, a 200-mW (23 dBm) 60-GHz power amplifier has been implemented in a standard 130-nm SiGe process technology, which, to date, is the highest reported output power in an SiGe process technology at millimeter-wave frequencies. The size of the output transformer is only 160times160 mum² and demonstrates the feasibility of efficient power combining and impedance transformation at millimeter-wave frequencies. The two-stage amplifier has 13 dB of compressed gain and achieves a power-added efficiency of 6.4% while combining the power of eight cascode amplifiers into a differential 100-Omega load. The amplifier supply voltage is 4 V with a quiescent current consumption of 300 mA     

应用于TD-SCDMA移动终端的单片InGaP/GaAs HBT功率放大器

报道了用于TD-SCDMA移动终端的高效率、高线性度HBT功率放大器的研制.该单片功率放大器采用两级放大结构,内部集成了输入匹配、级问匹配网络以及有源偏置电路,总芯片面积仅为0.91mmX 0.98mm.该功率放大器采用单电源3.4V供电,在高、低功率模式下,PAE分别为43%和116%,增益达到了28.5以及24dB.当输入QPSK调制信号时,在低输出功率以及高输出功率状态下,1.6MHz/3.2MHz中心频偏处,ACPR分别低于-45dBc/-56dBc和-39dBc/-50dBc.本芯片尺寸小,电压稳定性高,性能优越,为低成本化的大规模生产提供了能性.     

3–10-GHz Ultra-Wideband Low-Noise Amplifier Utilizing Miller Effect and Inductive Shunt–Shunt Feedback Technique

In this paper, we demonstrate an SiGe HBT ultra-wideband (UWB) low-noise amplifier (LNA), achieved by a newly proposed methodology, which takes advantage of the Miller effect for UWB input impedance matching and the inductive shunt-shunt feedback technique for bandwidth extension by pole-zero cancellation. The SiGe UWB LNA dissipates 25.8-mW power and achieves S₁₁ below -10 dB for frequencies from 3 to 14 GHz (except for a small range from 10 to 11 GHz, which is below -9 dB), flat S₂₁ of 24.6 plusmn 1.5 dB for frequencies from 3 to 11.6 GHz, noise figure of 2.5 and 5.8 dB at 3 and 10 GHz, respectively, and good phase linearity property (group-delay variation is only plusmn28 ps across the entire band). The measured 1-dB compression point (P₁ dB) and input third-order intermodulation point are -25.5 and -17 dBm, respectively, at 5.4 GHz.     

80-GHz Tuned Amplifier in Bulk CMOS

An 80-GHz six-stage common source tuned amplifier has been demonstrated using low leakage (higher V_T) NMOS transistors of a 65-nm digital CMOS process with six metal levels. It achieves power gain of 12 dB at 80 GHz with a 3-dB bandwidth of 6 GHz, noise figures (NF's) lower than 10.5 dB at frequencies between 75 and 81 GHz with the lowest NF of 9 dB. IP_{1 dB} is -21 dBm and IIP3 is -11.5 dBm. The amplifier consumes 27 mA from a 1.2 V supply. At V_DD = 1.5 V and 33 mA bias current, NF is less than 9.5 dB within the 3-dB bandwidth and reaches a minimum of 8 dB at 80 GHz.     

用于SDH STM-64光接收机的GaAs HBT限幅放大器

采用2μm GaAs HBT工艺实现了10Gb/s的限幅放大器.整个系统包括一级输入缓冲、三级放大、一级用于驱动50Ω传输线的输出缓冲和失调电压补偿回路四个部分.采用双电源供电,正电源为3.3V,负电源为-2V,功耗为500mW.在输出电压幅度保持恒定(单端峰峰值300mV)的条件下,输入动态范围约为38dB.芯片面积为1.15×0.7mm².     

一款适用于WCDMA标准的大动态范围SiGe HBT可变增益放大器设计

第三代移动通信标准WCDMA要求放大器增益可调,并且增益动态范围较大.根据这一要求给出了一种基于SiGe HBT具有高动态范围的可变增益放大器(VGA)设计.放大器为三级级联结构,第一级为输入缓冲级,第二级为增益控制级,最后为放大级.VGA的增益控制通过调整第二级的偏置实现.VGA在1.95 GHz频率下,在0～2.7 V增益控制电压变化下,具有44 dB增益变化范围,最大增益49 dB.在最大增益处最小噪声系数为2.584 dB,输入输出电压驻波比低于2,性能良好.